基于bt1120時序設計實現(xiàn)棋盤格橫縱向灰階圖數(shù)據(jù)輸出

• 一、bt1120介紹
• 二、代碼
• 三、bt1120中文建議書

一、bt1120介紹

bt1120的標準時序為1080p@60hz，其一幀數(shù)據(jù)主要是由消隱和有效數(shù)據(jù)構成，有效數(shù)據(jù)為YCbCr 4：2：2方式輸出，在數(shù)字行消隱還有兩種定時基準碼，一種在每個視頻數(shù)據(jù)塊的起始（SAV），另一種在每個視頻數(shù)據(jù)塊
的結束（EAV），其一幀數(shù)據(jù)還有兩場和一場兩種方式輸出，一幀格式如下圖所示。

逐行掃描系統(tǒng)中的幀時間期定時規(guī)范

圖像定時基準碼的比特分配
在EAV 和SAV輸出，其格式如下，在這兩個基準碼前還有三個固定數(shù)據(jù)其格式為 ff 00 00 EAV、
ff 00 0 SAV.

二、代碼

bt1120

module bt1120(//inputsclk,rst_n,data_in,//outputshcnt,vcnt,hsync,vsync,data_out,clk_out);input clk; input rst_n; input [15:0] data_in;output [11:0] hcnt; output [10:0] vcnt; output [15:0] data_out; output clk_out; output hsync; output vsync;reg [15:0] data_out;parameter HNUM = 12'd2200; // 1080p @30Hz 2200 @25hz 2640 parameter VNUM = 11'd1125; parameter HSYNC_END = 12'd276; parameter VSYNC_START = 11'd1121; parameter VSYNC_END = 11'd41; parameter EAV = 12'd4; parameter SAV = 12'd280; parameter EAV_PRE = 12'd1; parameter SAV_PRE = 12'd277;assign clk_out = ~clk;reg hsync; reg vsync; reg [11:0] hcnt; reg [10:0] vcnt;always @(posedge clk or negedge rst_n) beginif(!rst_n) beginhcnt<=12'd1;vcnt<=11'd1;endelse if(hcnt==HNUM) beginhcnt<=12'd1;if(vcnt==11'd1125)vcnt<=11'd1;elsevcnt<=vcnt+11'd1;endelsehcnt<=hcnt+12'd1; endalways @(posedge clk or negedge rst_n) beginif(!rst_n)hsync<=1'b0;else if(hcnt==HNUM)hsync<=1'b1;else if(hcnt==HSYNC_END)hsync<=1'b0;else; endalways @(posedge clk or negedge rst_n) beginif(!rst_n)vsync<=1'b0;else if(hcnt==HNUM) beginif(vcnt==VSYNC_START)vsync<=1'b1;else if(vcnt==VSYNC_END)vsync<=1'b0;else;endelse; endassign p3 = 1'b0^vsync^hsync; assign p2 = 1'b0^hsync; assign p1 = 1'b0^vsync; assign p0 = vsync^hsync;always @(posedge clk or negedge rst_n) beginif(!rst_n)data_out<=16'd0;else if(hcnt==SAV_PRE || hcnt==EAV_PRE)data_out<=16'hffff;else if(hcnt==EAV || hcnt==SAV)data_out<={1'b1,1'b0,vsync,hsync,p3,p2,p1,p0,1'b1,1'b0,vsync,hsync,p3,p2,p1,p0};else if(hcnt==SAV_PRE+12'd1 || hcnt==SAV_PRE+12'd2 || hcnt==EAV_PRE+12'd1 || hcnt==EAV_PRE+12'd2)data_out<=16'd0;else if(hcnt==EAV+12'd1)data_out<={~vcnt[6],vcnt[6:0],~vcnt[6],vcnt[6:0]};else if(hcnt==EAV+12'd2)data_out<={4'b1000,vcnt[10:7],4'b1000,vcnt[10:7]};else if(hsync==1'b0 && vsync==1'b0)data_out<=data_in;elsedata_out<=16'h1080; endendmodule

下面展示一些 內(nèi)聯(lián)代碼片。

test_img

module test_img(//inputsclk ,rst_n ,hcnt ,vcnt ,img_ctrl ,//outputsdata_out );input clk ; input rst_n ; input [11:0] hcnt ; input [10:0] vcnt ; input [3:0] img_ctrl ;output [15:0] data_out ;reg [15:0] data_out ;/********************************************************/ reg [15:0] data_checker ; reg [15:0] data_grayscale_c; reg [15:0] data_grayscale_l;//輸出 always @(*)begin if(img_ctrl == 4'b0000)begin //checkerboarddata_out = data_checker;end else if(img_ctrl == 4'b0001)begin //gray scale crosswisedata_out = data_grayscale_c;end else if (img_ctrl == 4'b0010) begin //gray scale lengthwaysdata_out = data_grayscale_l; endelse begin data_out <= data_checker;end end//checkerboard always @(posedge clk or negedge rst_n) beginif(!rst_n)data_checker<=1'b0;else if(vcnt[6]) beginif(hcnt[6])data_checker<={8'd16,8'd128};//{8'd16,8'd128};16'ha040;elsedata_checker<={8'd235,8'd128};//{8'd235,8'd128};16'h60a0;endelse beginif(hcnt[6])data_checker<={8'd235,8'd128};//{8'd235,8'd128};16'h4050;elsedata_checker<={8'd16,8'd128};//{8'd16,8'd128};16'hb0c0;end end//gray scale//crosswise reg [7:0] cnt ; wire add_cnt ; wire end_cnt ;reg [3:0] cnt_12 ; wire add_cnt_12 ; wire end_cnt_12 ;always @(posedge clk or negedge rst_n)begin if(!rst_n)begincnt <= 8'd1;end else if (hcnt == 12'd280) begincnt <= 8'd1;endelse if(add_cnt)begin if(end_cnt)begin cnt <= 8'd1;endelse begin cnt <= cnt + 8'd1;end endelse begincnt <= cnt;end end assign add_cnt = end_cnt_12; assign end_cnt = add_cnt && cnt == 8'd160;always @(posedge clk or negedge rst_n)begin if(!rst_n)begincnt_12 <= 4'd1;end else if (hcnt == 12'd280) begincnt_12 <= 4'd1;endelse if(add_cnt_12)begin if(end_cnt_12)begin cnt_12 <= 4'd1;endelse begin cnt_12 <= cnt_12 + 4'd1;end endelse begincnt_12 <= cnt_12;end end assign add_cnt_12 = hcnt>12'd280; assign end_cnt_12 = add_cnt_12 && cnt_12 == 4'd12;always @(posedge clk or negedge rst_n)begin if(!rst_n)begindata_grayscale_c <= 16'd0;end else begin data_grayscale_c <= {cnt,8'd128};end end//lengthwaysreg [7:0] cnt_l ; wire add_cnt_l ; wire end_cnt_l ;reg [3:0] cnt_12_l ; wire add_cnt_12_l ; wire end_cnt_12_l ;always @(posedge clk or negedge rst_n)begin if(!rst_n)begincnt_l <= 8'd1;end else if (vcnt == 11'd41) begincnt_l <= 8'd1;endelse if(add_cnt_l)begin if(end_cnt_l)begin cnt_l <= 8'd1;endelse begin cnt_l <= cnt_l + 8'd1;end endelse begincnt_l <= cnt_l;end end assign add_cnt_l = end_cnt_12_l; assign end_cnt_l = add_cnt_l && cnt_l == 8'd108;always @(posedge clk or negedge rst_n)begin if(!rst_n)begincnt_12_l <= 4'd1;end else if (vcnt == 11'd41) begincnt_12_l <= 4'd1;endelse if(add_cnt_12_l)begin if(end_cnt_12_l)begin cnt_12_l <= 4'd1;endelse begin cnt_12_l <= cnt_12_l + 4'd1;end endelse begincnt_12_l <= cnt_12_l;end end assign add_cnt_12_l = vcnt>11'd41 && hcnt == 12'd2200; assign end_cnt_12_l = add_cnt_12_l && cnt_12_l == 4'd10;always @(posedge clk or negedge rst_n)begin if(!rst_n)begindata_grayscale_l <= 16'd0;end else begin data_grayscale_l <= {cnt_l,8'd128};end end

三、bt1120中文建議書

https://blog.csdn.net/li_lys/article/details/124870664?utm_source=app&app_version=5.4.0&code=app_1562916241&uLinkId=usr1mkqgl919blen

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