基于FPGA的混沌信號(hào)發(fā)生器系統(tǒng)介紹:
由于模擬電路元器件的參數(shù)會(huì)受溫度、老化等環(huán)境原因影響，而混沌系統(tǒng)又是對(duì)初始值極度敏感的系統(tǒng)，因此使用模擬電路實(shí)現(xiàn)混沌系統(tǒng)的效果非常有限。而數(shù)字電路不存在器件溫度、老化問題，器件參數(shù)不會(huì)影響其結(jié)果，實(shí)現(xiàn)效果較模擬電路更加理想，故現(xiàn)階段使用數(shù)字點(diǎn)路實(shí)現(xiàn)混沌系統(tǒng)成為主流。目前有兩種實(shí)現(xiàn)方法，一種是基于歐拉算法、龍格庫塔的離散算法編寫底層硬件代碼實(shí)現(xiàn)混沌系統(tǒng)，另外一種是使用Matlab 的DSP BUILDER庫搭建混沌數(shù)字電路，自動(dòng)生成verilog代碼。兩種方法各有優(yōu)點(diǎn)，前者設(shè)計(jì)更加靈活但編程復(fù)雜，后者不需要編程但往往受器件約束。本文詳細(xì)介紹了使用的四階龍格庫塔算法實(shí)現(xiàn)混沌系統(tǒng)過程，實(shí)現(xiàn)了一個(gè)具有隱藏多穩(wěn)態(tài)吸引子的混沌系統(tǒng)發(fā)生器。圖1.1是該系統(tǒng)的整體硬件框架。PC端根據(jù)算法使用quartus II EDA軟件編寫硬件代碼并生成下載文件，通過下載器下載至 CycloneⅣ的EP4CE10F17C8N FPGA核心板，FPGA控制并輸送數(shù)字信息給ACM9767DAC模塊，由該模塊生成模擬信號(hào)再輸送給示波器顯示。

以洛倫茲系統(tǒng)為例，使用改進(jìn)的歐拉算法實(shí)現(xiàn) ，有不足的地方還望指正

module chaos_4D(clk,rst_n,x,y,z);input clk;input rst_n;output signed [31:0]x,y,z;parameter t= 12;//時(shí)間1/2^12reg signed [31:0] x_0 = 32'b0_00000_00000100000000000000000000; //初始值，由定點(diǎn)數(shù)表示一位符號(hào)位，五位整數(shù)位和26位小數(shù)位，初始值已經(jīng)被壓縮reg signed [31:0] y_0 = 32'b0_00000_00000010000000000000000000; //y_0=0reg signed [31:0] z_0 = 32'b0_00000_00000010000000000000000000; //z_0=0reg signed [31:0] c = 32'b0_00010_10101010101010101010101011; //8/3reg signed [31:0] xz_extend_6;//比例壓縮，由于怕計(jì)算過程內(nèi)部出現(xiàn)比五位整數(shù)位大的數(shù)，導(dǎo)致內(nèi)部計(jì)算溢出，x,y,z都?jí)嚎s64。例如dx = xy +z,將x,y,z壓縮64，原=原式變換為d64x = 64x*64y +64z等價(jià)于dx=32xy+z;即n項(xiàng)式要乘于32^（n-1） reg signed [31:0] xy_extend_6;//同上reg signed [31:0] fx ;//改進(jìn)歐拉算法中間值 reg signed [31:0] fy ; reg signed [31:0] fz ;reg signed [31:0] x_n_temp ;//計(jì)算的中間值，用來存儲(chǔ)x_n的值 reg signed [31:0] y_n_temp ; reg signed [31:0] z_n_temp ;reg signed [31:0] x_n ;//計(jì)算的中間值 reg signed [31:0] y_n ; reg signed [31:0] z_n ;reg signed [31:0] fx_temp ;//改進(jìn)歐拉算法的中間值 reg signed [31:0] fy_temp ; reg signed [31:0] fz_temp ;reg [2:0]state; reg cnt; reg flag;parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3;wire signed [63:0]xz_64;//兩個(gè)32位的數(shù)相乘是64位wire signed [63:0]xy_64;wire signed [63:0]cz_64;wire signed [31:0]ay;//用移位寄存器來計(jì)算整數(shù)乘wire signed [31:0]ax;wire signed [31:0]bx;wire signed [31:0]xz;/對(duì)xz_64位數(shù)進(jìn)行截取后的結(jié)果wire signed [31:0]xy;wire signed [31:0]cz;wire signed [31:0]x_temp;//結(jié)果，由于可能為負(fù)數(shù)，一般加上一個(gè)正數(shù)后才輸出，保證輸出全為正數(shù)wire signed [31:0]y_temp;wire signed [31:0]z_temp;assign ay = (y_n<<<3) + (y_n<<<1);//y*a //移位寄存器來進(jìn)行乘10操作assign ax = (x_n <<< 3) + (x_n<<<1) ; //x*a 同時(shí)assign bx = (x_n <<< 5) - (x_n <<< 2) ; // b*x//移位寄存器來進(jìn)行乘28操作，先乘32減去乘4assign xz_64 = x_n * z_n;//乘法assign xy_64 = x_n * y_n;assign cz_64 = c * z_n;assign xz = {xz_64[63],xz_64[56:26]} ;//截取規(guī)則為保留符號(hào)位，摒棄低26位小數(shù)位（可忽略）和高6位整數(shù)位（一般做了壓縮后，都是為0）assign xy = {xy_64[63],xy_64[56:26]} ;assign cz = {cz_64[63],cz_64[56:26]} ;always@(posedge clk or negedge rst_n)if(!rst_n)//復(fù)位beginflag <= 1;xz_extend_6 <= 0;xy_extend_6 <= 0;fx <= 0;fy <= 0;fz <= 0;x_n_temp <= 0;y_n_temp <= 0;z_n_temp <= 0;x_n <= x_0;y_n <= y_0;z_n <= z_0;fx_temp <= 0;fy_temp <= 0;fz_temp <= 0;cnt <= 0; state <= 0;endelsebegin case(state)s0:beginxz_extend_6 <= xz <<< 6; //乘64xy_extend_6 <= xy <<< 6; //乘64state <= state +1'b1;flag <= 0;ends1:beginfx <=-ax+ay;fy <= -xz_extend_6 + bx - y_n ;fz <= -cz + xy_extend_6;//改進(jìn)歐拉第一步操作，根據(jù)cnt的值對(duì)fx,fy,fz進(jìn)行更新if( cnt == 1 )//若已完成兩步操作，進(jìn)入到最后一步beginstate <= state + 2'd2 ;cnt <= 0;end else//進(jìn)入到下一步操作state <= state + 1'b1 ;ends2:beginx_n_temp <= x_n;//保存x_n的值y_n_temp <= y_n;z_n_temp <= z_n;x_n <= x_n + (fx>>>(t-1));//對(duì)x_n進(jìn)行關(guān)于改進(jìn)歐拉算法的計(jì)算y_n <= y_n + (fy>>>(t-1));z_n <= z_n + (fz>>>(t-1));cnt <= 1;fx_temp <= fx;//保存fx的值fy_temp <= fy;fz_temp <= fz;state <= s0;end s3:beginx_n <= x_n_temp + (fx>>>t) + (fx_temp>>>t);//改進(jìn)歐拉算法的結(jié)果y_n <= y_n_temp + (fy>>>t) + (fy_temp>>>t);z_n <= z_n_temp + (fz>>>t) + (fz_temp>>>t);state <= s0;flag <= 1;enddefault: beginx_n <= x_0;y_n <= y_0;z_n <= z_0;state <= s0;end endcaseendassign x_temp= (flag)?x_n:x_temp;//flag為1，x_n才能作為有效輸出，其余時(shí)候都是中間值assign y_temp= (flag)?y_n:y_temp;assign z_temp= (flag)?z_n:z_temp; assign x = x_temp+ 32'b0000_0100_0000_0000_0000_0000_0000_0000;//加個(gè)1保證輸出為正assign y = y_temp+ 32'b0000_0100_0000_0000_0000_0000_0000_0000;assign z = z_temp+ 32'b0000_0100_0000_0000_0000_0000_0000_0000;endmodule //tb文件 `timescale 1ns/1ns `define clock_period 20module gaijin_euler_tb;reg clock;reg Rst_n;wire [31:0]x,y,z;wire [11:0]x_n,y_n,z_n;assign x_n = x[27:16];assign y_n = y[27:16];assign z_n = z[27:16];chaos_4D fourD0(.clk(clock),.rst_n(Rst_n),.x(x),.y(y),.z(z));integer handle_x,handle_y,handle_z; integer i; initialbeginhandle_x = $fopen("data_x.txt");handle_y = $fopen("data_y.txt");handle_z = $fopen("data_z.txt");//handle_w = $fopen("data_w.txt");endinitial clock = 1'b1;always #(`clock_period/2) clock = ~clock;initialbeginRst_n = 1'b0;#(`clock_period*20+1)Rst_n = 1'b1;for(i=0;i<400000;i=i+1'b1)begin#(`clock_period)begin$fdisplay(handle_x,"%d",x);//將數(shù)據(jù)保存為txt文件，十六進(jìn)制格式的數(shù)據(jù)，可以通過matlab觀察相位圖$fdisplay(handle_y,"%d",y);$fdisplay(handle_z,"%d",z);// $fdisplay(handle_w,"%d",w);endend$stop;end endmodule

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