作者：桂。

時間：2018-02-05?20:50:54

鏈接：http://www.cnblogs.com/xingshansi/p/8419452.html?

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一、仿真思路

　　設(shè)計低通濾波器（5階，6個系數(shù)），濾波器特性：

?借助低通濾波器對信號進行濾波：

二、VIVADO仿真

　　首先利用MATLAB生成定點補碼：

%=============設(shè)置系統(tǒng)參數(shù)==============% f1=500; %設(shè)置波形頻率 f2=3600; Fs=8000; %設(shè)置采樣頻率 L=1024; %數(shù)據(jù)長度 N=16; %數(shù)據(jù)位寬 %=============產(chǎn)生輸入信號==============% t=0:1/Fs:(1/Fs)*(L-1); y=sin(2*pi*f1*t)+sin(2*pi*t*f2); y_n=round(y*(2^(N-3)-1)); %N比特量化;如果有n個信號相加，則設(shè)置（N-n） %=================畫圖==================% a=10; %改變系數(shù)可以調(diào)整顯示周期 stem(t,y_n); axis([0 L/Fs/a -2^N 2^N]); %顯示 %=============寫入外部文件==============% fid=fopen('sin_data.txt','w'); %把數(shù)據(jù)寫入sin_data.txt文件中，如果沒有就創(chuàng)建該文件 for k=1:length(y_n)B_s=dec2bin(y_n(k)+((y_n(k))<0)*2^N,N);for j=1:Nif B_s(j)=='1'tb=1;elsetb=0;endfprintf(fid,'%d',tb);endfprintf(fid,'\r\n'); endfprintf(fid,';'); fclose(fid);

　　vivado的testbench：

`timescale 1ns / 1ps module tb;// Inputslogic Clk;logic rst;// Outputslogic signed [23:0] Yout;//Generate a clock with 10 ns clock period. initial Clk <= 0;always #5 Clk = ~Clk;//Initialize and apply the inputs. //-------------------------------------// parameter data_num = 32'd1024; integer i = 0; reg [15:0] Xin[1:data_num]; reg [15:0] data_out;initial beginrst = 1; #20rst = 0; #40$readmemb("D:/PRJ/vivado/simulation_ding/009_lpf6tap/matlab/sin_data.txt",Xin); endalways @(posedge Clk) beginif(rst)begindata_out <= 0;endelse begindata_out <= Xin[i];i <= i + 8'd1;end end fir_6tap uut ( .Clk(Clk), .Xin(data_out), .Yout(Yout) ); endmodule

　　子模塊 fir_6tap：

`timescale 1ns / 1ps module fir_6tap(input Clk,input signed [15:0] Xin,output reg signed [23:0] Yout);//Internal variables.wire signed [7:0] H0,H1,H2,H3,H4,H5;wire signed [23:0] MCM0,MCM1,MCM2,MCM3,MCM4,MCM5,add_out1,add_out2,add_out3,add_out4,add_out5;wire signed [23:0] Q1,Q2,Q3,Q4,Q5;//filter coefficient initializations. //H = [-2 -1 3 4].assign H0 = -15;assign H1 = 19 ;assign H2 = 123;assign H3 = 123;assign H4 = 19;assign H5 = -15;//Multiple constant multiplications.assign MCM5 = H5*Xin;assign MCM4 = H4*Xin;assign MCM3 = H3*Xin;assign MCM2 = H2*Xin;assign MCM1 = H1*Xin;assign MCM0 = H0*Xin;//addersassign add_out1 = Q1 + MCM4;assign add_out2 = Q2 + MCM3;assign add_out3 = Q3 + MCM2; assign add_out4 = Q4 + MCM1; assign add_out5 = Q5 + MCM0; //flipflop instantiations (for introducing a delay).DFF dff1 (.Clk(Clk),.D(MCM5),.Q(Q1));DFF dff2 (.Clk(Clk),.D(add_out1),.Q(Q2));DFF dff3 (.Clk(Clk),.D(add_out2),.Q(Q3));DFF dff4 (.Clk(Clk),.D(add_out3),.Q(Q4));DFF dff5 (.Clk(Clk),.D(add_out4),.Q(Q5)); //Assign the last adder output to final output.always@ (posedge Clk)Yout <= add_out5;endmodule

　　DFF：

`timescale 1ns / 1ps module DFF(input Clk,input [23:0] D,output reg [23:0] Q);always@ (posedge Clk)Q = D;endmodule

　　主要電路圖（4階為例）：

　　仿真結(jié)果，與MATLAB測試一致：

總結(jié)

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