Original address:?http://blog.ednchina.com/riple/74826/message.aspx

在使用SignalTAP II的過程中，我經(jīng)常發(fā)現(xiàn)一些用于調(diào)試的邏輯（比如調(diào)試用的計(jì)數(shù)器）會(huì)被優(yōu)化掉，不能出現(xiàn)在調(diào)試波形中。在Altera的一篇文檔中，發(fā)現(xiàn)了以下關(guān)鍵信息:?

In the logic synthesis stage, the Quartus II software may optimize away signals that you are trying to analyze with the SignalTap II Embedded Logic Analyzer. If this occurs, you will see a compilation error. You can force the Quartus II software to preserve these signals by adding the keep or preserve attribute in the source HDL to the signals you want to monitor.

The?keep?attribute is used for a wire or net node. For example:
In Verilog:
??? wire my_wire /* synthesis keep = 1 */:
In VHDL:
??? signal my_signal: bit;
??? attribute syn_keep : boolean;
??? attribute syn_keep of my_signal: signal is true;

The?preserve?attribute is used for a register. For example:
In Verilog:
??? reg my_reg /* synthesis preserve = 1 */:
In VHDL:
??? signal my_reg: stdlogic;
??? attribute preserve : boolean;
??? attribute preserve of my_signal: signal is true;

謝謝, riple!!

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