Verilog有限狀態(tài)機(2)

HDLBits鏈接

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前言

繼續(xù)更新狀態(tài)機小節(jié)的習(xí)題。

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題庫

題目描述6：

Solution6：

module top_module(input in,input [3:0] state,output [3:0] next_state,output out); //parameter A=0, B=1, C=2, D=3;// State transition logic: Derive an equation for each state flip-flop.assign next_state[A] = (state[A]&~in) | (state[C] & ~in);assign next_state[B] = (state[A]&in) | (state[D]&in) | (state[B]&in);assign next_state[C] = (state[B]&~in) | (state[D]&~in);assign next_state[D] = (state[C]&in);// Output logic: assign out = (state[D]);endmodule

本題中作者想讓我們以one-hot(獨熱碼)的編碼邏輯來完成。一般狀態(tài)機為了方便編碼都是設(shè)置為二進(jìn)制；但若狀態(tài)轉(zhuǎn)移是按順序進(jìn)行轉(zhuǎn)移的話，我們可以使用格雷碼，因為兩相鄰狀態(tài)之間只變化1bit，這樣可以節(jié)約功耗；若想提升速度，可以使用one-hot編碼，因為每次僅需判斷一位，這是用寄存器資源換組合邏輯資源，以達(dá)到更高的速度。

題目描述7：

題目與上題相同，區(qū)別為異步復(fù)位，復(fù)位至狀態(tài)A。

Solution7：

module top_module(input clk,input in,input areset,output out); //parameter A=2'd0,B=2'd1,C=2'd2,D=2'd3;reg [1:0] state,next_state;always @(*)begincase(state)A:beginif(in == 0)beginnext_state <= A;endelse beginnext_state <= B;endendB:beginif(in == 0)beginnext_state <= C;endelse beginnext_state <= B;endendC:beginif(in == 0)beginnext_state <= A;endelse beginnext_state <= D;endendD:beginif(in == 0)beginnext_state <= C;endelse beginnext_state <= B;endendendcaseendalways @(posedge clk,posedge areset)beginif(areset)beginstate <= A;endelse beginstate <= next_state;endendassign out = (state == D);endmodule

題目描述8：

題目同上題，講復(fù)位改為同步復(fù)位。

Solution8：

module top_module(input clk,input in,input reset,output out); //parameter A=2'd0,B=2'd1,C=2'd2,D=2'd3;reg [1:0] state,next_state;always @(*)begincase(state)A:beginif(in == 0)beginnext_state <= A;endelse beginnext_state <= B;endendB:beginif(in == 0)beginnext_state <= C;endelse beginnext_state <= B;endendC:beginif(in == 0)beginnext_state <= A;endelse beginnext_state <= D;endendD:beginif(in == 0)beginnext_state <= C;endelse beginnext_state <= B;endendendcaseendalways @(posedge clk)beginif(reset)beginstate <= A;endelse beginstate <= next_state;endendassign out = (state == D);endmodule

題目描述9：

Solution9：

module top_module (input clk,input reset,input [3:1] s,output fr3,output fr2,output fr1,output dfr ); parameter A2=3'd0,B1=3'd1,B2=3'd2,C1=3'd3,C2=3'd4,D1=3'd5;reg [2:0] state,next_state;always @(*)begincase(state)A2:next_state <= s[1]?B1:A2;B1:next_state <= s[2]?C1:(s[1]?B1:A2);B2:next_state <= s[2]?C1:(s[1]?B2:A2);C1:next_state <= s[3]?D1:(s[2]?C1:B2);C2:next_state <= s[3]?D1:(s[2]?C2:B2);D1:next_state <= s[3]?D1:C2;default:next_state <= 'x;endcaseendalways @(posedge clk)beginif(reset)beginstate <= A2;endelse beginstate <= next_state;endendalways @(*)begincase(state)A2:{fr3,fr2,fr1,dfr} = 4'b1111;B1:{fr3,fr2,fr1,dfr} = 4'b0110;B2:{fr3,fr2,fr1,dfr} = 4'b0111;C1:{fr3,fr2,fr1,dfr} = 4'b0010;C2:{fr3,fr2,fr1,dfr} = 4'b0011;D1:{fr3,fr2,fr1,dfr} = 4'b0000;default:{fr3,fr2,fr1,dfr} = 'x;endcaseendendmodule

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小結(jié)

今天先更新這幾道題目，重點是one-hot編碼部分，了解其與格雷碼的優(yōu)缺點。

總結(jié)

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