Verilog有限狀態機(4)

HDLBits鏈接

---

前言

今天繼續更新狀態機小節的習題。

---

題庫

題目描述1：

One-hot FSM

獨熱編碼，根據狀態轉移圖輸出下一狀態與結果。

Solution1：

module top_module(input in,input [9:0] state,output [9:0] next_state,output out1,output out2);parameter S0 = 4'd0;parameter S1 = 4'd1;parameter S2 = 4'd2;parameter S3 = 4'd3;parameter S4 = 4'd4;parameter S5 = 4'd5;parameter S6 = 4'd6;parameter S7 = 4'd7;parameter S8 = 4'd8;parameter S9 = 4'd9;assign next_state[0] = ~in & (state[S0] | state[S1] | state[S2] | state[S3] | state[S4] | state[S7] | state[S8] | state[S9]);assign next_state[1] = in & (state[S0] | state[S8] | state[S9]);assign next_state[2] = in & state[S1];assign next_state[3] = in & state[S2];assign next_state[4] = in & state[S3];assign next_state[5] = in & state[S4];assign next_state[6] = in & state[S5];assign next_state[7] = in & (state[S6] | state[S7]);assign next_state[8] = ~in & state[S5];assign next_state[9] = ~in & state[S6];assign out1 = (state[S8] | state[S9]);assign out2 = (state[S7] | state[S9]);endmodule

題目描述2：

PS/2 packet parser

首先，這道題目中作者表明in的第3位為1時，狀態機啟動，其他兩位可能為1或0，注意，這里不允許重疊檢測，根據作者給出的時序圖，大家應該就可以寫出狀態機了。

Solution2：

module top_module(input clk,input [7:0] in,input reset, // Synchronous resetoutput done); //parameter BYTE_FIRST = 2'd0;parameter BYTE_SECOND = 2'd1;parameter BYTE_THIRD = 2'd2;parameter WAIT = 2'd3;reg [1:0] state,next_state;// State transition logic (combinational)always @(*)begincase(state)BYTE_FIRST:beginnext_state <= BYTE_SECOND;endBYTE_SECOND:beginnext_state <= BYTE_THIRD;endBYTE_THIRD:beginif(in[3] == 1'b1)beginnext_state <= BYTE_FIRST;endelse beginnext_state <= WAIT;endendWAIT:beginif(in[3] == 1'b1)beginnext_state <= BYTE_FIRST;endelse beginnext_state <= WAIT;endendendcaseend// State flip-flops (sequential)always @(posedge clk)beginif(reset)beginstate <= WAIT;endelse beginstate <= next_state;endend// Output logicassign done = (state == BYTE_THIRD);endmodule

題目描述3：

PS/2 packet parser and datapath

這道題目相比上一道多了數據位輸出，當done信號為1時，輸出24bit的數據，這24bit的數據高8位，中8位，低8位分別從in[3]為1開始計起，依次輸出。done信號為0的時候不關心數據信號。高8位輸出僅當下一狀態為BYTE_SECOND才開始，此處可以簡化判斷邏輯，大家可以注意一下。

Solution3：

module top_module(input clk,input [7:0] in,input reset, // Synchronous resetoutput [23:0] out_bytes,output done); //parameter BYTE_FIRST = 2'd0;parameter BYTE_SECOND = 2'd1;parameter BYTE_THIRD = 2'd2;parameter DONE = 2'd3;reg [1:0] state,next_state;reg [23:0] out_bytes_reg;// FSM from fsm_ps2always @(posedge clk)beginif(reset)beginstate <= BYTE_FIRST;endelse beginstate <= next_state;endendalways @(*)begincase(state)BYTE_FIRST:beginif(in[3])beginnext_state <= BYTE_SECOND;endelse beginnext_state <= BYTE_FIRST;endendBYTE_SECOND:beginnext_state <= BYTE_THIRD;endBYTE_THIRD:beginnext_state <= DONE;endDONE:beginif(in[3])beginnext_state <= BYTE_SECOND;endelse beginnext_state <= BYTE_FIRST;endendendcaseendalways @(posedge clk)beginif(next_state == BYTE_SECOND)beginout_bytes_reg[23:16] <= in;endelse if(next_state == BYTE_THIRD)beginout_bytes_reg[15:8] <= in;endelse if(next_state == DONE)beginout_bytes_reg[7:0] <= in;endelse beginout_bytes_reg <= 24'd0;endend// New: Datapath to store incoming bytes.assign done = (state == DONE);assign out_bytes = out_bytes_reg;endmodule

---

結語

今天就先更新這三題吧，今天上了數分課發現拉下好多課程，希望自己期末能過吧，哈哈哈，之后要好好復習了。若代碼有錯誤希望大家及時指出，我會盡快改正。

總結

以上是生活随笔為你收集整理的HDLBits答案(17)_Verilog有限状态机(4)的全部內容，希望文章能夠幫你解決所遇到的問題。

如果覺得生活随笔網站內容還不錯，歡迎將生活随笔推薦給好友。