线性稳压器的基本类型
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線性電壓穩(wěn)壓器的分類?
線性電壓穩(wěn)壓器是按照導通組件技術進行分類，包括：
NPN-Darlington、NPN、PNP、PMOS 及 NMOS 穩(wěn)壓器。
表 1 顯示不同的類型以及一般最小電壓差與靜態(tài)電流特性。
PNP 雙極體晶體管一般被運用于低壓降的應用，主要是因為這類晶體管很容易就能夠達到低壓降，
然而，它會產(chǎn)生高靜態(tài)電流，而且效率不高，因此不適用于以發(fā)揮最高效率為首要考慮的應用。
PMOS 裝置經(jīng)過大量心力的開發(fā)，目前的效能已超越大多數(shù)的雙極體裝置。
NMOS 導通組件的最大優(yōu)勢是它的電阻不高，不過，閘極驅(qū)動的困難卻使得這類導通組件在應用中顯得并不理想。
NMOS LDO （如TPS74901）能夠在 3A 輸出電流的情況下達到 120mV 最小電壓差。
與 PMOS 拓樸裝置不同的是，輸出電容器對于回路穩(wěn)定性的影響不大。
不論是搭配多顆電容器或甚至不搭配電容器，德州儀器推出的多款 NMOS LDO 都能穩(wěn)定的運作。
NMOS的瞬時響應也優(yōu)于 PMOS 拓樸，對于低輸入電壓的應用更是如此。
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Circuit Operation:
The load current is sensed by the "I SENSE" resistor, which develops a voltage that is directly related to the current.
This voltage is level shifted (and amplified) by the differential amplifier.
The voltage at the output of the differential amplifier is a ground-referenced signal that is proportional to the load current.
This "load current" signal coming from the differential amplifier is applied to the inverting input of the current limit error amplifier,
while the non-inverting input is connected to a reference voltage.
The value of this reference voltage would be equal to the voltage at the output of the differential amplifier
when the regulator is driving maximum current (at the current limit point).
Note that as long as the load current is below the limit threshold, the output of the current error amplifier is high
(and the voltage error amplifier keeps the regulator in constant voltage mode).
When the load current reaches the limit threshold, the output of the current error amplifier drops low
and starts sinking current away from the output of the voltage error amplifier (this puts the regulator in constant current mode).
When current limiting occurs, the regulator output voltage will drop below its nominal value,
which will be sensed by the voltage error amplifier as an undervoltage condition.
The voltage error amplifier will drive its output high in an attempt to raise the output voltage,
but the current error amplifier can sink all of the current coming from the voltage error amplifier.
Like the thermal limiter, the current limiter overrides the voltage error amplifier to prevent damage to the IC.
The load line shown in Figure 8 illustrates how the output voltage is held constant up to the point where the load current reaches the limit value,
where the regulator crosses over into constant current mode.
When operating in constant current mode, the IC regulates the load current to the "limit" value,
which means the output voltage may be any value down to zero volts.
It should be made clear that the thermal limiter can always override the current limiter,
and can reduce the output voltage and current to any value necessary to maintain a junction temperature of about 160°C.
For example, if the LP2952 (which is rated for 250 mA) is shorted from the output to ground,
a current will flow from the output which is greater than 250 mA but less than 530 mA (see "Current Limit specification on the data sheet).
However, if the input voltage is high enough to generate sufficient power to activate the thermal limiter,
that current will drop off as the LP2952 regulates its die temperature to about 160°C.
Important:
Current limit circuits are (by necessity) very high-speed circuits, and input bypass capacitors?on the regulator
are always recommended to prevent possible device failure due to interaction with the input source impedance.
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Super beta PNP Circuitry
The simplified schematic diagram of Micrel’s medium?and high current monolithic LDOs appears as?Figure 4-1.
The high current path from input to output?through the pass transistor is in bold.
The bandgap?reference and all other circuitry is powered via the?Enable Circuit, which allows for “zero” current draw?when disabled.
The reference voltage is compared?to the sampled output voltage fed back by R1 and?R2.
If this voltage is less than the bandgap reference,?the op amp output increases.
This increases the current?through driver transistor Q2, which pulls down?on the base of Q1, turning it on harder.
If Q1’s base?current rises excessively, the voltage drop across R3?enables Q3, which in turn limits the current through?Q2.
Die temperature is monitored, and if it becomes excessive, the thermal shutdown circuit activates,?clamping the base of Q2 and shutting down Q1.
The?flag circuit looks at the output voltage sample and?compares it to a reference set 5% lower.
If the sample?is even lower, the flag comparator saturates the open?collector flag transistor, signaling the fault condition.
Dropout Voltage
The Super beta PNP family of low-dropout regulators?offers typical dropout voltages of only 300mV?across the output current range.
This low dropout is?achieved by using large and efficient multicelled PNP?output transistors, and operating them in their highbeta?range well below their capacity.
Dropout voltage?in the Super beta PNP regulators is determined by?the saturation voltage of the PNP pass element.
As?in all bipolar transistors, the saturation voltage is proportional to the current through the transistor.
At light?loads, the dropout voltage is only a few tens of millivolts.?At moderate output currents, the dropout rises?to 200 to 300mV.
At the full rated output, the typical?dropout voltage is approximately 300mV for most of?the families.
Lower cost versions have somewhat?higher dropout at full load, generally in the 400 to?500mV range.
The data sheet for each device graphs?typical dropout voltage versus output current.?
Ground Current
Micrel’s Super beta PNP process allows these?high current devices to maintain very high transistor?beta—on the order of 100 at their full rated current.
This contrasts with competitive PNP devices that suffer?with betas in the 10 to 30 range. This impacts?regulator designs by reducing wasteful ground current.
Micrel’s beta of 100 translates into typical full?load ground currents of only 1% of your output.
The?data sheet for each device graphs typical ground current?versus output current.
When linear regulators approach dropout, generally?due to insufficient input voltage, base drive to?the pass transistor increases to fully saturate the transistor.
With some older PNP regulators, the ground?current would skyrocket as dropout approached.
Micrel’s Super beta PNP regulators employ saturation?detection circuitry which limits base drive when?dropout-induced saturation occurs, limiting ground?current.
Fully Protected
Micrel regulators are survivors. Built-in protection?features like current limiting, overtemperature?shutdown, and reversed-input polarity protection allow?LDO survival under otherwise catastrophic situations.
Other protection features are optionally available,?such as overvoltage shutdown and a digital error?flag.
Current Limiting
Current limiting is the first line of defense for a?regulator.
It operates nearly instantaneously in the?event of a fault, and keeps the internal transistor, its?wire bonds,
and external circuit board traces from?fusing in the event of a short circuit or extremely heavy?output load.
The current limit operates by linearly?clamping the output current in case of a fault.
For?example, if a MIC29150 with a 2A current limit encounters?a shorted load, it will pass up to 2A of current?into that load.
The resulting high power dissipation?(2A multiplied by the entire input voltage) causes?the regulator’s die temperature to rise,
triggering the?second line of defense, overtemperature shutdown.
Overtemperature Shutdown
As the output fault causes internal dissipation?and die temperature rise, the regulator approaches?its operating limits.
At a predetermined high temperature,?the regulator shuts off its pass element, bringing?output current and power dissipation to zero.
The?hot die begins cooling. When its temperature drops?below an acceptable temperature threshold, it automatically?re-enables itself.
If the load problem has?been addressed, normal operation resumes.
If the?short persists, the LDO will begin sourcing current,?will heat up, and eventually will turn off again.
This?sequence will repeat until the load is corrected or input?power is removed.
Although operation at the verge?of thermal shutdown is not recommended,
Micrel has?tested LDOs for several million ON/OFF thermal?cycles without undue die stress.
In fact, during reliability ?testing, regulators are burned-in at the thermal?shutdown-cycle limit.
Reversed Input Polarity
Protection from reversed input polarity is important?for a number of reasons.
Consumer products?using LDOs with this feature survive batteries inserted?improperly or the use of the wrong AC adapter.
Automotive?electronics must survive improper jump starting.?
All types of systems should last through initial?production testing with an incorrectly inserted (backward)?regulator.
By using reversed input protected?regulators, both the regulator and its load are protected?against reverse polarity, which limits reverse?current flow.
Overvoltage Shutdown
Most Micrel LDOs feature overvoltage shutdown. ?
If the input voltage rises above a certain predetermined?level, generally between 35V and 40V, the?control circuitry disables the output pass transistor.
This feature allows the regulator to reliably survive?high voltage (60V or so—see the device data sheet?for the exact limit) spikes on the input regardless of?output load conditions.
The automotive industry calls?this feature “Load-Dump Protection”1 and it is crucial?to reliability in automotive electronics.?
Many of Micrel’s regulator families offer a version?with a digital error flag output.
The error flag?monitors the output voltage and pulls its open collector?(or drain) output low if the voltage is too low.
The ?definition of “too low” ranges from about –5% to –8%?below nominal output, depending upon the device?type.
The flag comparator is unaffected by low input?voltage
or a too-light or too-heavy load (although a?too-heavy load generally will cause the output voltage?to drop, triggering the flag).
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The most attractive device for the external pass?element is the N-channel power MOSFET (see Figure?4-5).
Discrete N-channel MOSFET prices continue?to decrease (due to high volume usage),
and?the race for lower and lower ON resistance works in?your favor.
The N-channel MOSFET, like the?P-channel MOSFET, reduces ground current.
With?device ON resistance now below 10mW, dropout voltages?below 100mV are possible with output currents?in excess of 10A.
Even lower dropouts are possible?by using two or more pass elements in parallel.?
Unfortunately, full gate-to-source enhancement?of the N-channel MOSFET
requires an additional 10V?to 15V above the required output voltage.
Controlling?the MOSFET’s gate using a second higher voltage?supply requires additional circuitry and is clumsy?at best.
“線性”串聯(lián)穩(wěn)壓器（見圖1）通常包括一個基準電壓源、一個比例輸出電壓與基準電壓比較環(huán)節(jié)、
一個反饋放大器和一個串聯(lián)調(diào)整管組成（雙極型晶體管或FET 管）組成，用放大器控制穩(wěn)壓器的壓降維持要求的輸出電壓值。
例如，如果負載電流下降，會引起輸出電壓顯著上升，誤差電壓增大，
放大器的輸出上升，調(diào)整管兩端的電壓會增加，因此輸出電壓回到其原始值。
圖1 基本的增強型PMOS LDO
在圖1中，誤差放大器和PMOS晶體管構成壓控電流源。
輸出電壓VOUT按分壓比（R1，R2）成比例下降，并且將其與基準電壓（VREF）比較。
誤差放大器的輸出控制增強型PMOS晶體管。
穩(wěn)壓器的“壓差”是指輸出電壓與輸入電壓之間的壓差，
如果此輸入電壓繼續(xù)減小那么該電路便不能穩(wěn)壓。
通常認為當輸出電壓下降到低于標稱值100 mV時是達到的目標。
表征這LDO穩(wěn)壓器的關鍵指標取決于負載電流和調(diào)整管的PN結溫度。
壓差對穩(wěn)壓器分為三類：標準穩(wěn)壓器、準LDO和LDO 。
標準穩(wěn)壓器，通常使用NPN調(diào)整管，通常輸出管的壓降大約為2V。
準LDO穩(wěn)壓器，通常使用達林頓復合管結構（見圖2）以便實現(xiàn)由一只NPN晶體管和一只PNP晶體管組成的調(diào)整管。
這種復合管的壓降，VSAT (PNP)＋VBE (NPN) 通常大約為1V —比LDO高但比標準穩(wěn)壓器低。
圖2 準LDO電路
LDO穩(wěn)壓器通常根據(jù)壓差要求作最佳選擇，通常壓差在100 mV～200 mV 范圍。
然而，LDO的缺點是其接地引腳的電流通常比準LDO或標準穩(wěn)壓器大。
標準穩(wěn)壓器比其它類型穩(wěn)壓器具有較大的壓差，較大的功耗和較低的效率。
大多數(shù)情況下可使用LDO穩(wěn)壓器代替標準穩(wěn)壓器，但是應該考慮到LDO穩(wěn)壓器的最大輸入電壓指標比標準穩(wěn)壓器低。
此外，有些LDO需要精心挑選外部電容器以保持穩(wěn)定性。
這三種類型穩(wěn)壓器在帶寬和動態(tài)穩(wěn)定性考慮因素方面也有些不同。
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LDO結構
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在圖1中，調(diào)整管是PMOS晶體管。然而，穩(wěn)壓器可能使用各種類型的調(diào)整管，
因此可以根據(jù)所使用的調(diào)整管類型對LDO分類。
不同結構和特性的LDO具有不同的優(yōu)點和缺點。
四種類型調(diào)整管示例如圖3所示，
包括NPN雙極型晶體管、PNP雙極型晶體管、
復合晶體管和PMOS晶體管。
對于給定的電源電壓，雙極型調(diào)整管可提供最大的輸出電流。
PNP優(yōu)于NPN，因為PNP的基極可以與地連接，必要時使晶體管完全飽和。
NPN的基極只能與盡可能高的電源電壓連接，從而使最小壓降限制到一個VBE結壓降。
因此，NPN管和復合調(diào)整管不能提供小于1V的壓差。
然而它們在需要寬帶寬和抗容性負載干擾時非常有用（因為它們具有低輸出阻抗ZOUT特性）。
PMOS和PNP晶體管可以快速達到飽和，從而能使調(diào)整管電壓損耗和功耗最小，從而允許用作低壓差、低功耗穩(wěn)壓器。
PMOS調(diào)整管可以提供盡可能最低的電壓降，大約等于RDS(ON)×IL。它允許達到最低的靜態(tài)電流。
PMOS調(diào)整管的主要缺點是MOS 晶體管通常用作外部器件—
特別當控制大電流時—從而使IC構成一個控制器，而不能構成一個自身完整的穩(wěn)壓器。
一個完整穩(wěn)壓器的總功耗是??? PD = (VIN – VOUT) IL + VINIGND
上面關系式的第一部分是調(diào)整管的功耗；
第二部分是電路控制器部分的功耗。
有些穩(wěn)壓器的接地電流，特別是那些用飽和雙極型晶體管作調(diào)整管的穩(wěn)壓器，會在上電期間達到峰值。
低飽和型穩(wěn)壓壓器（LDO）的方框圖
隨著便攜式設備（電池供電）在過去十年間的快速增長，
象原來的業(yè)界標準 LM340 和 LM317 這樣的穩(wěn)壓器件已經(jīng)無法滿足新的需要。
這些穩(wěn)壓器使用NPN 達林頓管，在本文中稱其為NPN 穩(wěn)壓器（NPN regulators）。
預期更高性能的穩(wěn)壓器件已經(jīng)由新型的
低壓差（Low-dropout）穩(wěn)壓器（LDO）和
準LDO穩(wěn)壓器（quasi-LDO）實現(xiàn)了。
NPN 穩(wěn)壓器（NPN regulators）
在NPN穩(wěn)壓器（圖1：NPN穩(wěn)壓器內(nèi)部結構框圖）的內(nèi)部
使用一個 PNP管來驅(qū)動 NPN 達林頓管（NPN Darlington pass transistor），
輸入輸出之間存在至少1.5V～2.5V的壓差（dropout voltage）。
這個壓差為：Vdrop ＝ 2Vbe ＋Vsat（NPN 穩(wěn)壓器） （1）
LDO 穩(wěn)壓器（LDO regulators）
在LDO(Low Dropout)穩(wěn)壓器（圖2：LDO穩(wěn)壓器內(nèi)部結構框圖）中，導通管是一個PNP管。
LDO的最大優(yōu)勢就是PNP管只會帶來很小的導通壓降，滿載（Full-load）的跌落電壓的典型值小于500mV，
輕載（Light loads）時的壓降僅有10～20mV。LDO的壓差為：
Vdrop ＝ Vsat （LDO 穩(wěn)壓器） （2）?
準LDO 穩(wěn)壓器（Quasi-LDO regulators）
準LDO（Quasi-LDO）穩(wěn)壓器（圖3： 準 LDO 穩(wěn)壓器內(nèi)部結構框圖）
已經(jīng)廣泛應用于某些場合，例如：5V到3.3V 轉換器。
準LDO介于 NPN 穩(wěn)壓器和 LDO 穩(wěn)壓器之間而得名， 導通管是由單個PNP 管來驅(qū)動單個NPN 管。
因此，它的跌落壓降介于NPN穩(wěn)壓器和LDO之間：Vdrop ＝ Vbe ＋Vsat （3）
穩(wěn)壓器的工作原理（Regulator Operation）
所有的穩(wěn)壓器，都利用了相同的技術實現(xiàn)輸出電壓的穩(wěn)定（圖4：穩(wěn)壓器工作原理圖）。
輸出電壓通過連接到誤差放大器（Error Amplifier）反相輸入端（Inverting Input）
的分壓電阻（Resistive Divider）采樣（Sampled），
誤差放大器的同相輸入端（Non-inverting Input）連接到一個參考電壓Vref。
參考電壓由IC內(nèi)部的帶隙參考源(Bandgap Reference)產(chǎn)生。
誤差放大器總是試圖迫使其兩端輸入相等。
為此，它提供負載電流以保證輸出電壓穩(wěn)定：
Vout = Vref(1 + R1 / R2) （4）
性能比較(Performance Comparison)
NPN，LDO和準LDO在電性能參數(shù)上的最大區(qū)別是：
跌落電壓（Dropout Voltage）和地腳電流（Ground Pin Current）。
跌落電壓前文已經(jīng)論述。為了便于分析，我們定義地腳電流為Ignd （參見圖4），并忽略了IC到地的小偏置電流。
那么，Ignd等于負載電流IL除以導通管的增益。
NPN 穩(wěn)壓器中，達林頓管的增益很高（High Gain）， 所以它只需很小的電流來驅(qū)動負載電流IL。
這樣它的地腳電流Ignd也會很低，一般只有幾個mA。
準LDO也有較好的性能，如國半（NS）的LM1085能夠輸出3A的電流卻只有10mA的地腳電流。
然而，LDO的地腳電流會比較高。
在滿載時，PNP管的β值一般是15～20。也就是說LDO的地腳電流一般達到負載電流的7%。
NPN穩(wěn)壓器的最大好處就是無條件的穩(wěn)定，大多數(shù)器件不需額外的外部電容。
LDO在輸出端最少需要一個外部電容以減少回路帶寬（Loop Bandwidth）
及提供一些正相位轉移（Positive Phase Shift）補償。
準LDO一般也需要有輸出電容，但容值要小于LDO的并且電容的ESR局限也要少些。?
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10.3串聯(lián)、開關式穩(wěn)壓電路?
10.3.1 線性串聯(lián)穩(wěn)壓電路?
1、線性串聯(lián)型穩(wěn)壓電路的工作原理?
穩(wěn)壓二極管的缺點是工作電流較小，穩(wěn)定電壓值不能連續(xù)調(diào)節(jié)。線性串聯(lián)型穩(wěn)壓電源工作電流較大，
輸出電壓一般可連續(xù)調(diào)節(jié)，穩(wěn)壓性能優(yōu)越。目前這種穩(wěn)壓電源已經(jīng)制成單片集成電路，
廣泛應用在各種電子儀器和電子電路之中。線性串聯(lián)型穩(wěn)壓電源的缺點是損耗較大、效率低。?
(1) 線性串聯(lián)型穩(wěn)壓電源的構成?
線性串聯(lián)型穩(wěn)壓電源的工作原理可以用圖10.19加以說明。?
顯然，VO =VI- VR，當VI增加時，R受控制而增加，使VR增加，從而在一定程度上抵消了VI增加對輸出電壓的影響。
若負載電流IL增加，R受控制而減小，使VR減小，從而在一定程度上抵消了因IL增加，使VI減小，對輸出電壓減小的影響。?? ? ? ? ??
在實際電路中，可變電阻R是用一個三極管來替代的，
控制基極電位，從而就控制了三極管的管壓降VCE，VCE相當于VR。
要想輸出電壓穩(wěn)定，必須按電壓負反饋電路的模式來構成串聯(lián)型穩(wěn)壓電路。
典型的串聯(lián)型穩(wěn)壓電路如圖10.20所示。
它由調(diào)整管、放大環(huán)節(jié)、比較環(huán)節(jié)、基準電壓源幾個部分組成。?
1．輸入電壓變化，負載電流保持不變?
輸入電壓VI的增加，必然會使輸出電壓VO有所增加，
輸出電壓經(jīng)過取樣電路取出一部分信號VF與基準源電壓VREF比較，獲得誤差信號ΔV。
誤差信號經(jīng)放大后，用VO1去控制調(diào)整管的管壓降VCE增加，從而抵消輸入電壓增加的影響。?
2．負載電流變化，輸入電壓保持不變?
負載電流IL的增加，必然會使輸入電壓VI有所減小，輸出電壓VO必然有所下降，
經(jīng)過取樣電路取出一部分信號VF與基準電壓源VREF比較，獲得的誤差信號使VO1增加，
從而使調(diào)整管的管壓降VCE下降，從而抵消因IL增加使輸入電壓減小的影響。?
3．輸出電壓調(diào)節(jié)范圍的計算?
調(diào)節(jié)R2顯然可以改變輸出電壓。????
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一，來自百度的說明????
??? ?LDO是low dropout regulator，意為低壓差線性穩(wěn)壓器，是相對于傳統(tǒng)的線性穩(wěn)壓器來說的。傳統(tǒng)的線性穩(wěn)壓器，如78xx系列的芯片都要求輸入電壓要比輸出電壓高出2v~3V以上，否則就不能正常工作。但是在一些情況下，這樣的條件顯然是太苛刻了，如5v轉3.3v,輸入與輸出的壓差只有1.7v，顯然是不滿足條件的。針對這種情況，才有了LDO類的電源轉換芯片。
二，什么是線性穩(wěn)壓器
線性穩(wěn)壓器主要包括普通線性穩(wěn)壓器和LDO（Low Dropout Regulator，低壓差線性穩(wěn)壓器）兩種類型，它們的主要區(qū)別是：普通線性穩(wěn)壓器（如常見的78系列三端穩(wěn)壓器）工作時要求輸入與輸出之間的壓差值較大（一般要求在2～3V以上），功耗較高；而LDO工作時要求輸入與輸出之間的壓差值較小（可以為IV以下甚至更低），功耗較低。
（1）線性穩(wěn)壓器基本工作原理
線性穩(wěn)壓器是通過輸出電壓反饋，經(jīng)誤差放大器等組成的控制電路來控制調(diào)整管的管壓降VDD（即壓差）來達到穩(wěn)壓的目的，其原理框圖如圖1所示。特點是VIN必須大于VOUT，調(diào)整管工作在線性區(qū)（線性穩(wěn)壓器從此得名）。輸入電壓的變動或負載電流的變化引起輸出電壓變動時，通過反饋及控制電路，改變VDO的大小，使輸出電壓VOUT基本不變。
普通線性穩(wěn)壓器和LD0的工作原理是一致的，不同的是，二者采用的調(diào)整管結構不同，從而使LD0比普通線性穩(wěn)壓器壓差更小，功耗更低。
有些液晶顯示器中使用的線性穩(wěn)壓器設有輸出控制端，也就是說，這種穩(wěn)壓器輸出電壓受控制端的控制。圖2所示是可控穩(wěn)壓器的內(nèi)部框圖。
三，LDO初步認識
???? LDO 是一種線性穩(wěn)壓器。線性穩(wěn)壓器使用在其線性區(qū)域內(nèi)運行的晶體管或 FET，從應用的輸入電壓中減去超額的電壓，產(chǎn)生經(jīng)過調(diào)節(jié)的輸出電壓。所謂壓降電壓，是指穩(wěn)壓器將輸出電壓維持在其額定值上下 100mV 之內(nèi)所需的輸入電壓與輸出電壓差額的最小值。
V壓降=MIN（Vin-Vout）|Vout+100mv
????? 正輸出電壓的LDO（低壓降）穩(wěn)壓器通常使用功率晶體管（也稱為傳遞設備）作為 PNP。這種晶體管允許飽和，所以穩(wěn)壓器可以有一個非常低的壓降電壓，通常為 200mV 左右；與之相比，使用 NPN 復合電源晶體管的傳統(tǒng)線性穩(wěn)壓器的壓降為 2V 左右。負輸出 LDO 使用 NPN 作為它的傳遞設備，其運行模式與正輸出 LDO 的 PNP設備類似。
???? 更新的發(fā)展使用 MOS 功率晶體管，它能夠提供最低的壓降電壓。使用功率MOS，通過穩(wěn)壓器的唯一電壓壓降是電源設備負載電流的 ON 電阻造成的。如果負載較小，這種方式產(chǎn)生的壓降只有幾十毫伏。
???? 新的LDO線性穩(wěn)壓器可達到以下指標：輸出噪聲30μV，PSRR為60dB，靜態(tài)電流6μA（TI的TPS78001達到Iq=0.5uA），電壓降只有100mV(TI量產(chǎn)了號稱0.1mV的LDO)。LDO線性穩(wěn)壓器的性能之所以能夠達到這個水平，主要原因在于其中的調(diào)整管是用P溝道MOSFET，而普通的線性穩(wěn)壓器是使用PNP晶體管。P溝道MOSFET是電壓驅(qū)動的，不需要電流，所以大大降低了器件本身消耗的電流；另一方面，采用PNP晶體管的電路中，為了防止PNP晶體管進入飽和狀態(tài)而降低輸出能力， 輸入和輸出之間的電壓降不可以太低；而P溝道MOSFET上的電壓降大致等于輸出電流與導通電阻的乘積。由于MOSFET的導通電阻很小，因而它上面的電壓降非常低。
????? 如果輸入電壓和輸出電壓很接近，最好是選用LDO穩(wěn)壓器，可達到很高的效率。所以，在把鋰離子電池電壓轉換為3V輸出電壓的應用中大多選用LDO穩(wěn)壓器。雖說電池的能量最後有百分之十是沒有使用，LDO穩(wěn)壓器仍然能夠保證電池的工作時間較長，同時噪音較低。
???? 如果輸入電壓和輸出電壓不是很接近，就要考慮用開關型的DCDC了，因為從上面的原理可以知道，LDO的輸入電流基本上是等于輸出電流的，如果壓降太大，耗在LDO上能量太大，效率不高。
?????DC-DC轉換器包括升壓、降壓、升/降壓和反相等電路。DC-DC轉換器的優(yōu)點是效率高、可以輸出大電流、靜態(tài)電流小。隨著集成度的提高，許多新型DC-DC轉換器僅需要幾只外接電感器和濾波電容器。但是，這類電源控制器的輸出脈動和開關噪音較大、成本相對較高。
???? 總的來說，升壓是一定要選DCDC的，降壓，是選擇DCDC還是LDO，要在成本，效率，噪聲和性能上比較。
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挑選線性穩(wěn)壓器 (LDO)
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固定輸出電壓的LDO具有內(nèi)部回饋網(wǎng)路，輸出電壓可調(diào)的LDO要使用外部回饋網(wǎng)路，以此提供更大彈性。
一些輸出可調(diào)的元件同時也具有內(nèi)部回饋網(wǎng)路，因此也可作為固定輸出版本使用。
- V?IN(MIN)?> 2.5V : PMOS類型的 LDO
- V?IN(MIN)>1.0V : 使用外加偏置電壓或內(nèi)置電荷泵升壓偏置的NMOS型 LDO
LDO design techniques for small spaces
A key challenge to the ultra-miniaturization of electronic systems is power management. As any electronics engineer knows, when overall system sizes shrink the amount of area available for energy storage and energy conversion shrinks with it. This is happening in many market-growing applications, such as implantable medical devices, Internet-of-things (IoT) electronics, and wearable electronics. While the size of the electronics continues to scale, the batteries and capacitors required to store energy are not keeping up. The consequence is that often times the area required for energy storage and power management dominates the overall form factor of the final product.
Due to these area limitations energy must be stored in an efficient form. Often times the most efficient form is at a higher potential and with significant noise components. A voltage regulator – such as an LDO – is then required to regulate this supply voltage down to the level at which the system operates.
A key figure of merit in low power LDO design is current efficiency. Current efficiency is defined as the ratio of Iload to Itotal. This ratio is the percentage of overall power drawn from the power supply that is delivered to the load. For high power applications it is common for this number to exceed 99 percent. However, this is very different in low power design. If, for example, the total load current is 10uA, every 1uA of quiescent current in the LDO results in a 10% drop in current efficiency. In an already power constrained system this loss in efficiency can be catastrophic. As such, design methods that minimize the overall LDO quiescent current are critical. A properly designed LDO will maintain overall system efficiency and long battery life, minimizing the need for large energy storage elements.
A Short LDO Design Overview
Figure 1 shows an LDO block diagram utilizing an NMOS pass transistor.
Consider applications where the unregulated power supply voltage (Vsply) is much greater than the regulated output voltage (Vreg).
Here, a simple NMOS pass transistor architecture is usually the best choice.
LDO block diagram with NMOS pass transistor.
This architecture has many desirable properties, two of which are trivial frequency compensation and a small FET area.
A small FET area is a result of the higher mobility of charge carriers in NMOS FETs (electrons) versus that of PMOS FETs (holes).
The ease of frequency compensation is due to the dominant pole being at the gate of the NMOS pass transistor instead of at the output node.
LDOs are typically two pole systems, with some architectures including a zero and / or an additional high frequency pole.
The NMOS LDO shown in figure 1 is a simple two pole system.
Therefore, stability is achieved by setting the frequency of pole P1 more than one decade below pole P2.
As long as the two poles, P1 and P2, are well separated this LDO will be closed-loop stable.
This is assuming that the error amplifier is a simple OTA with a single dominant pole at the output node.
Once the output capacitor size (Cout) is determined (set by high frequency load transient requirements, such as digital logic switching), pole P1 can be calculated.
P1 is set by the product of the error amplifiers output impedance (ro) and the compensation capacitor (Cc).
By increasing ro we are able to simultaneously achieve low P1 frequency and high loop gain, both very desirable traits.
It is important to remember that in an OTA design, high output impedance does not cost extra current just extra area.
This enables the OTA, and correspondingly the LDO, quiescent current to be the minimum value required for unity gain bandwidth.
This is an application specific requirement that sets the base line for quiescent current in a traditional LDO architecture.
In many applications a quiescent current of only 100nA to 200nA is sufficient.
This results in a current efficiency that is greater than 98 percent.
It is worth noting that slew-rate enhanced LDOs are capable of going below this minimum current, but at a significant cost in terms of size and complexity.
Therefore, in an NMOS LDO, both stability and low quiescent current go hand-in-hand.
But nothing comes for free. The NMOS LDO has one very large shortcoming.
The minimum supply voltage (or overhead voltage) is Vgs(MN) + Vsat(MN) + Vreg
which is approximately equal to 2Vsat(MN) + Vth + Vreg.
Even if a native threshold NMOS transistor is used (Vth = ～0V) this is double the overhead voltage of using a PMOS pass transistor.
This is a major shortcoming that prevents the NMOS LDO from being used in many applications.
It is also worth noting that use of a native threshold NMOS pass transistor is typically not advised.
This is because across process corners these devices are very difficult to fully turn off, resulting in Vreg drifting up.
The alternative to an NMOS LDO architecture is a PMOS LDO.
The PMOS LDO has the distinct advantage over the NMOS LDO of true “l(fā)ow-dropout” operation.
This topology is capable of regulating the supply down to just one Vsat over the output voltage (<100mV is readily achievable).
This, however, comes at the cost of significantly more challenging design tradeoffs.
Many of these design tradeoffs are the consequence of pole position P1 and P2 swapping locations.
While on the surface this seems like a small difference, it actually has very large implications to error amplifier design and overall LDO quiescent current.
These implications and more will be covered in a future post to come soon.
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總結
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