【筆記】 數字集成電路設計

書籍：《數字集成電路——電路、系統與設計》（第二版）

第一章 引論

1. 數字設計中需解決的問題

摩爾定律

技術突破才能推動摩爾定律

特征尺寸

28nm是傳統制程和先進制程的分界點

存儲器容量

存儲器的容量增大，以為著功耗增大，意味著穩定性下降（發熱）。如果想要實現更大容量的突破，需要尋找新技術或者新架構使功耗不能超過功耗紅線

晶圓尺寸

晶圓尺寸增加，單位硅片數量增加，所需的技術越先進，最終成品芯片價格也越低

• 技術突破
• 大直徑的硅片可以大大提高成品率

2. 集成電路質量評價

1. 成本

$$集成電路=固定成本（研發、設備、公司、人工）+可變成本（制作芯片的成本）$$

$$可變成本=\frac{芯片成本+芯片測試成本+封裝成本}{最終測試成品率}$$

$$芯片成本=\frac{晶圓成本}{每個圓片的芯片數\times 芯片成品率}$$

$$每個圓片的芯片數=\frac{\pi \times 圓片半{徑}^2}{芯片面積}?\frac{\pi \times 圓片直徑}{\sqrt{2\times 芯片面積}}$$

$$芯片成品率={(1+\frac{電位面積的缺陷數\times 芯片面積}{\alpha })}^{?\alpha }$$

注：、

①$\alpha$是取決于制造工藝復雜行參數，常取值3

②單位面積缺陷數常取值0.5~1個缺陷/cm2

③
$$芯片成本=f(芯片面積{)}^4$$

2. 穩定性與功能性

噪聲：電容耦合、電感耦合、地線耦合

3. 性能

性能常與時鐘周期、時鐘頻率相關

重點：延時

傳播延時：輸入和輸入波形的50%翻轉點之間的時間

如圖：

定義傳播時間$t_p$?為
$$t_p=\frac{t_{pLH}+t_{pHL}}{2}$$
一般而言，

①$t_{pLH}$和$t_{pHL}$不會完全相等

②如果要求傳輸延時＜$t$，則意味著$$t_{pLH}<t$$并且$$t_{pHL}<t$$

上升時間$t_r$?

下降時間$t_f$

4. 功耗和能耗

取決的因素太多了。

常常有：瞬時功耗、峰值功耗（研究電源線尺寸）、平均功耗（研究冷卻或者對電池的要求）

3. 數字IC基本概念

1. 電壓傳輸特性VTC（DC傳輸曲線）

可接受的高電壓、低電壓區域：$V_{IH}$和$V_{IL}$?定義為VTC增益=-1的點

2. 噪聲容限

3. 再生性

保證一個受干擾的信號經過若干個組合邏輯之后依舊回到一個額定電平（高或者低，不是不確定態）

4. 抗干擾能力

5. 方向性

6.扇入和扇出

扇入和扇出個數和一些延遲有關

4. IC全定制流程

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