1.前言

本文是對K64 datasheet 之ENET部分的功能描述，將對每個部分進行詳細說明

2.Ethernet MAC frame formats

MAC幀組成格式

（1）7字節前導碼：如按最低位先傳則為0x55 0x550x550x550x550x55；

（2）起始幀定界符(SFD)：如按最低位先傳則為0XD5；

（3）2個地址域：包括源MAC地址和目的MAC地址；

（4）VLAN-tagged ：可選，占4字節

（5）長度或類型域：代表有效負荷的長度或者類型，以太網802.3組幀為例，如果小于0X05DC（1500字節）則為長度信息，如果大于0X0600（1536字節）則為類型信息

常見的類型為：IPV4，ARP等

（6）有效載荷：最小為42 octets（帶有VALAN-tagged）,46 octets（不帶有VALAN-tagged），最大載荷為1500 octets

（7）填充域：有效載荷不足42 octets（帶有VALAN-tagged）,46 octets（不帶有VALAN-tagged），則填充

（8）CRC值：4字節循環冗余校驗

注：

[1]幀長度不包括Preamble和SFD，幀最小長度為64字節，最大長度為1518字節

[2]除去 6 octets的 Destination address+6 octsts Source address+2 octets Length/type+4octets FCS = 18 octets，因此有效載荷需要至少46 octets，需填充0~46octets

[3]可選的是VLAN-tagged 可以插入到MACSource address和Length/type之間4字節，構成VLAN-tagged MAC 幀

MAC幀定義

Pause Frames

接收端產生一個pause frame指示當前傳輸遇到擁堵，發送端需要停止發送數據

Magic packets

用于實現遠程喚醒，當偵測到magic packet，主機會被喚醒

3.IP and higher layers frame format

舉例來說IP數據報指定了Ethernet幀的有效負荷，TCP數據報又在IP數據報中指定了有效負荷

Ethernet types

IPv4 datagram format

IPv6 datagram format

Internet Control Message Protocol (ICMP) datagram format

User Datagram Protocol (UDP) datagram format

TCP datagram format

4. IEEE 1588 message formats

Adjustable timer module

ENET時間戳時鐘源既可以來自外部ENET_1588_CLKIN PAD ，也可以來自內部ENET PLL 。最好選擇整形值如3ns產生精準計時

通過專用校準邏輯定時器被校準來同步遠端master時鐘作為本地系統的參考時鐘

Adjustable timer implementation

Transmit timestamping

Receive timestamping

Time synchronization

5. MAC receive

Collision detection in half-duplex mode

Preamble processing

MAC core允許任意長度的preample，也允許是0長度，如果preample后SFD的首個字節不是0x55也不是0xd5則丟棄

MAC address check

目的地址bit0區分了不同的地址：

（1）If bit 0 is 0, the MAC address is an individual (unicast) address.
（2）If bit 0 is 1, the MAC address defines a group (multicast) address.
（3）If all 48 bits of the MAC address are set, it indicates a broadcast address.

Frame length/type verification: payload length check

If the length/type is less than 0x600 and NLC is set, the MAC checks the payload lengthand reports any error in the frame status word and interrupt bit PLR

If the length/type is greater than or equal to 0x600, the MAC interprets the field as a typeand no payload length check is performed

The length check is performed on VLAN and stacked VLAN frames. If a padded frame isreceived, no length check can be performed

Frame length/type verification: frame length check
When the receive frame length exceeds MAX_FL bytes, the BABR interrupt is generatedand the RxBD[LG] bit is set.

VLAN frames processing

VLAN frames have a length/type field set to 0x8100 immediately followed by a 16-BitVLAN control information field.

Pause frame termination

The receive engine terminates pause frames and does not transfer them to the receiveFIFO

CRC check

The CRC-32 field is checked and forwarded to the core FIFO interface ifENETn_RCR[CRCFWD] is cleared and ENETn_RCR[PADEN] is set

Frame padding removal

Recieve flushing

RX flushing prevents frames in the RX FIFO from being blocked

6 MAC transmit

Frame payload padding

The IEEE specification defines a minimum frame length of 64 bytes

MAC address insertion

CRC-32 generation

Inter-packet gap (IPG)

Collision detection and handling — half-duplex operationonly

A collision occurs on a half-duplex network when concurrent transmissions from two ormore nodes take place.

7. Full-duplex flow control operation

8 Magic packet detection

Magic packet detection wakes a node that is put in power-down mode by the nodemanagement agent

9. IP accelerator functions

Checksum calculation

The IP and ICMP, TCP, UDP checksums are calculated with one's complementarithmetic summing up 16-bit values

Additional padding processing

32-bit Ethernet payload alignment

The data FIFOs allow inserting two additional arbitrary bytes in front of a frame. Thisextends the 14-byte Ethernet header to a 16-byte header, which leads to alignment of the
Ethernet payload

IPv4 fragments

IPv6 support

10. Resets and stop controls

Hardware reset

Soft reset

Hardware freeze

Graceful stop

During a graceful stop, any currently ongoing transactions are completed normally andno further frames are accepted

11 IEEE 1588 functions

Adjustable timer module

Transmit timestamping

Receive timestamping

Time synchronization

12 FIFO thresholds

Receive FIFO

Transmit FIFO

13 Loopback options

14 Legacy buffer descriptors

To support the Ethernet controller on previous Freescale devices, legacy FEC buffer descriptors are available

15 Enhanced buffer descriptors

This section provides a description of the enhanced operation of the driver/DMA via thebuffer descriptors

16 Client FIFO application interface

The FIFO interface is completely asynchronous from the Ethernet line, and the transmitand receive interface can operate at a different clock rate

17 FIFO protection

Transmit FIFO underflow

Transmit FIFO overflow

Receive FIFO overflow

18 Reference clock

The input clocks to the ENET module must meet the specifications in the following table

19 PHY management interface

MDIO frame format

MDIO clock generation

The MDC clock is generated from the internal bus clock divided by the valueprogrammed in ENETn_MSCR[MII_SPEED].

MDIO operation

To perform an MDIO access, set the MDIO command register (ENETn_MMFR)according to the description provided in MII Management Frame Register(ENETn_MMFR).

To check when the programmed access completes, read the ENETn_EIR[MII] field.

20 Ethernet interfaces

The following Ethernet interfaces are implemented:

-Fast Ethernet MII (Media Independent Interface)
-RMII 10/100 using interface converters/gaskets

The following table shows how to configure ENET registers to select each interface

RMII interface

MII Interface — transmit

MII interface — receive

總結

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