1、Single Choice: Given the following FIFO and rules, how deep does the FIFO need to be to prevent underflow or overflow?

RULES:

clk_A=25MHz;

clk_B=100MHz;

en_B is periodically asserted: period is 4us, dutycycle is 25%

Pick ONE option

A. 100 entries

B. 75 entries

C. FIFO will overflow anyway

D. 10 entries

解：B

2、Assuming a=1'b1; b=1'b0 what's the final values of a and b?

① always@(posedge clk) begin a=b; b=a; end	② always@(posedge clk) a=b; always@(posedge ?clk) b=a;	③ always@(posedge clk) begin a<=b; b<=a; end	④ always@(posedge ?clk) a<=b; always@(posedge ?clk) b<=a;
a= ?? b= ??	a= ?? b= ??	a= ?? b= ??	a= ?? b= ??

解：

1、a=0 b=0

2、? 我猜每次仿真結果都不一樣，always執行順序不同

3、a= 0 b=1

4、A=0 B=1

【Verilog HDL】賦值語句之阻塞賦值方式與非阻塞賦值方式_李銳博恩的博客-CSDN博客_verilog 阻塞賦值

3、What are commonly used techniques to reduce dynamic power in low power design?

Pick ONE OR MORE options

A. Bus signal encoding, bus decoding (5 points)

B. Clock gating

C. Power gating

D. Dynamic voltage and frequency scaling(DVFS)

E. Body biasing

解：查了一下感覺選abcde

BCD我知道

A 總線編解碼，大概就是通過編碼來減少信號翻轉率來降低功耗

Bus encoding/decoding apparatus and method - 百度學術https://xueshu.baidu.com/usercenter/paper/show?paperid=1r4y0rv0mr4f0g804v2k0tk0yk051550

A bus encoding/decoding apparatus and method for a low power digital signal processor (DSP), which uses a narrow data bus, is provided. The apparatus for encoding n bits of data of a data bus, includes a conditional inverting unit for inverting each of (n1) lower bits of n data when the most significant bit of the n bits of data is 1, a storage unit for storing the last n bits of data which is output to the bus, and a first exclusive OR operating unit for performing a bitwise exclusive OR operation on the lower (n1) bits or data, which has been inverted by the conditional inverting unit, and the lower (n1) bits of the n data, which has been stored in the storage unit, wherein the most significant bit of the n bits of data and (n1) bits of data, which is obtained as the result of the bitwise exclusive OR operation performed by the first exclusive OR operating unit, are output. Accordingly, interface problems with a core and overhead for an additional circuit can be reduced by removing the additional circuit for determining whether to invert data and an extra line, which are used in the conventional BI and BITS coding methods, thereby decreasing the power consumption and the area of a chip.

??????

D基體偏壓

重新定義低功耗、小尺寸FPGA-EDN 電子技術設計物聯網AI、嵌入式視覺、硬件安全、5G通信、工業和汽車自動化等新興應用正在重新定義開發人員設計網絡邊緣產品的硬件要求。https://www.ednchina.com/news/202005261413.html

FD-SOI工藝讓萊迪思的工程師能夠開發全新電路設計，充分發揮該工藝的固有優勢。其優勢之一就是FD-SOI支持可編程基體偏壓（body bias），這是一種位于晶體管基體上的塊電阻，能讓開發人員在晶體管運行期間進行動態調節。萊迪思的研發團隊發明的可編程基體偏壓，能夠根據設計的功耗和散熱管理需要，讓器件以高性能模式或低功耗模式運行。只需通過軟件開關即可控制運行模式。開發人員通過對基體偏壓進行編程實現高性能或低功耗之間的切換，可以優化 FPGA 的功耗/性能，更好地滿足應用的功耗和散熱管理需求。這不僅有助于降低電池供電的網絡邊緣設備的功耗，還能降低工業和數據中心等應用的電力成本。根據萊迪思估算，基于Nexus平臺的FPGA的功耗將比同類競品最多減少75%。

Bus encoding/decoding apparatus and method - 百度學術https://xueshu.baidu.com/usercenter/paper/show?paperid=1r4y0rv0mr4f0g804v2k0tk0yk051550

4、There is a triangle andon it there are 3 ants, one on each corner and they are free to move alongsides of triangle. What is probability that they will collide?

Pick ONE option

A. 1/8

B. 1/4

C. 3/8

D. 3/4

不想做這種東西

5、Complete the blanks inthe following question with the appropriate answer.

Select the appropriate asynchronous technical terms tothe corresponding sequence number.

CDC Check Clock Domain Crossing Check.

MTBF Check Mean Time Between Failure Check.

Glitch Check Combinational logic will cause glitch violationin sync path, it can be covered by STA Make sure no combinational logic beforea synchronizer.

Reconvergence Check: Signals synced by a groupsynchronizers can't merged into combinational logic immediately.

B2B Check: Two beat approach by flops are usually usedto handle asynchronous paths. But there is no quantized parameters to calculateMTBF by this approach.

Async Timing Check Async path timing status is notcovered by STA We use scripts to capture related timing to check these paths.

解：這圖好糊 、

6、Complete the blanks inthe following question with the appropriate answer.

There is a FIFO, at the input side, there will be atmost 80 valid input out of 100 cycles; at the output side there will be at least 8 available slots out of 10 cycles, please specify what is the minimized FIFO depth for this case.

Depth=_____106____

160*（80/100）- 160*（10/100）*（8/10）=128-12.8=106

?有空畫一遍

7、The following schematicshows datapath operators going into a register. From power perspective, figureout the inefficient part and draw a new schematic with your fix.

這D觸發器的q和q‘沒寫，先當q‘做吧

時鐘門控終極指南 - 知乎https://zhuanlan.zhihu.com/p/390828391

8 、There is a counter can down count from 60 to 0. When the count reaches 0, the count will alarm. There are 4 buttonson the counter (they can all be treated as pulse signals). Users are allowed topress merely 1 button each time. When the counter is alarming, press ‘add’ or ‘clear’buttons will stop alarming.

Button 'start'：press 'start' button,the counter will start downcount to 0.

Button 'clear'：press 'clear' button,the counter will be back to 60 and stop counting.

Button 'hold'：press 'hold' button, thecounter will stop countering, until press 'start' or 'clear' button ('add'button doesn't work when hold).

Button 'add'

press 'add' button, the counter will add 10 (Forexample, when the counter is 20, press 'add' then the counter will go back to 30. When the counter is 54, press 'add' then the counter will go back to 60.)

Please draw the finite state machine diagram

Please describe the counter in verilog using the ftmyou design in question 1(clock signal: clk, reset signal: rst_n) Output alarm(when the counter is arming, alarm=1). Output [5:0] counter_num from (60 to 0)

Please use below module definition to start with:

module downcounter(input? clk,input? rst_n,//funcbuttonsinput? start,input? clear,input? hold,input? add,output? alarm,output[5:0] counter_num);endmodule

ADD狀態轉移不知道畫的對不對

9、Suppose there is a logfile

The file's content is like: <MESSAGE LEVEL>_<MESSAGE_TYPE>_<MESSAGE_ CONTENT>

<MESSAGE_ LEVEL> should be "ERROR" or"WARNING" or "INFO"

<MESSAGE_TYPE> should be "TYPE" plusan integer number.

Please write a function named as printErrors to parsethe log, filter out required information and print some messages. Given astring logPath representing the log file path.

The requirements are:

a. The output messages should be ERROR level and theirMESSAGE_CONTENT should contain “NVIDIA_SOC”

b. Sorted the output order by MODULE_TYPE number

c. Use any script language you like.

###

Example 1:

log file.

ERROR_TYPE1_NVIDIA

INFO_TYPE1_NVIDIA SOC

ERROR_ TYPE4_THIS_IS_NVIDIA_SOC

WARNING_TYPE2_SOC

ERROR_TYPE1_SOC

ERROR_TYPE1_NVIDIA_SOC_TEAM

ERROR_TYPE4_NVIDIA_SOC

ERROR_TYPE12_NVIDIA_SOC

Example 2:

log file:

ERROR_TYPE1_NVIDIA

ERROR_TYPE12_NVIDIA_SOC

ERROR_TYPE1_Nvidia_soc

INFO_TYPE2_NVIDIA_SOC TEAM

ERROR TYPE12 NVIDIA SOC

###

Please provide your answer in the following editor

學完tcl在寫

10、Gate level logic netlist_ais optimized to netlist_b in back-end flow. And they are checked by formalcheck tool to prove whether they are functional equivalence. Please answer belowquestions.

1.What is the concept of combinational and sequential logic?Please classify A/B/C/D cells in below netlist_a schematic, which belong tocombinational logic and which belongs to sequential logic?

組合邏輯

時序邏輯

?bcd組合邏輯，a時序邏輯

2. If the value vector 110 is applied to the leftthree flops D pin After 1 cycle what is the D pin value of the reg_d in netlist_a/netlist_b?

3. Please estimate if above netlists are functionequivalent or not according to the netlist schematics and explain why?

不等效吧

第一個化簡得 ：第一個看不清，到底是vdd還是gnd？

假設是vdd，結果是a+b^c

如果是gnd，結果是a+b'c

第二個化簡得：a'+b^c

但不管是啥，a的路徑都不等價吧

11、3-stages pipelinecircuit shown as below.

The clock period is 0.9

The clock uncertainty is 0.1

The cell delay for F1/F2/F3 from CP-> Q are 0.15

The library setup require time for F1/F2/F3 are 0.1

1. Please calculate the setup slack between F1 and F2

?寫錯了 slack減反了，應該是-0.25ns

2. Please describe what's clock skew and suggest how to fix the setup violation between F1 and F2 with clock skew

?換一個速度快的寄存器，降低溫度，降低時鐘頻率，加流水線，縮短關鍵路徑，在f2時鐘路徑上加buffer

3. Please recalculate the slack between F2 and F3 after the setup violation between F1 and F2 are fixed to 0

【STA專題四】時序約束 - 知乎

setup slack = 0.9-0.15-0.1 = 0.75

12、Please use NAND2 gates to create new logic signal as below: (Use as less gates as possible) New_ logic= ECO_SELECT? Original_logic & mask: original logic;

?

?=[o’+(m+E')']’

13、Design a sequence(10100) detector. The logic with single bit input and single bit output. When detectinginput bit with the sequence of 10100 output pulse with one cycle of 1'b1,otherwise output keeps 1'b0. (No need to write RTL code, just provide aschematic diagram or a state machine flow chart.)

?輸出補一下斜杠，我忘寫了

14、Design a block (WriteVerilog code) with below requirement:

Block interfaces: data_in[31:0], data_ in_valid, data_out[31:0],data_out_valid, clock, reset_;

Function: Input package of data_in and output packageof data_out both include 4 bytes of data, and we expect that data_out containsthe 4 bytes data from the same position but in different input cycle. (i.e.output cycle 0 contains the lowest bytes from input cycle 0 to 3; output cycle1 contains to second lowest bytes from input cycle 0 to 3; output cycle 2contains second highest bytes from input cycle 0 to 3; output cycle 3 containshighest bytes from input cycle 0 to 3; output cycle 4 contains lowest bytesfrom input cycle 4 to8...)

Timing requirement: data_out and data_out_valid need direct flop-driven.

【舊文】面試手撕代碼真題詳解-窄傳輸【開卷】海思面試手撕代碼真題詳解-窄傳輸https://mp.weixin.qq.com/s/cR7cgt5mfWtsCyWEPvyHrg有空寫

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FPGA/IC筆試——雜七雜八 - 一曲挽歌 - 博客園

2022英偉達（NVIDA）實習生筆試（ASIC PD崗位）_桐桐花的博客-CSDN博客_英偉達筆試

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