這是畢業第一年的時候寫的一個項目程序，貢獻出來，供大家學習，交流，不做商用。

這是fpga做的圖像中值濾波，圖像的分辨率是256*256。以下是詳細東西，有這個算法的詳細思考過程，和程序，還有做出來的效果。效果是根據fpga算法用matlab仿真出來的。

以下是項目涉及的程序：

/*求最小值中的最大值。 */ `timescale 1ns/1psmodule max_of_3(//inputvclk,vsync,hsync,vden,min_x1,min_x2,min_x3,//outputvsync_out,hsync_out,vden_out,max_of_min ); input vclk; input vsync,hsync,vden; input [23:0] min_x1,min_x2,min_x3; output [23:0] max_of_min; output vsync_out,hsync_out,vden_out; reg [23:0] max_of_min=24'h0; reg vsync_reg,hsync_reg,vden_reg;always@(posedge vclk) beginif(min_x1>min_x2)beginif(min_x3>min_x1)beginmax_of_min<=min_x3;endelsebeginmax_of_min<=min_x1;endend elsebeginif(min_x3>min_x2)beginmax_of_min<=min_x3;endelse beginmax_of_min<=min_x2;endend end /****Delay Signals************************/ always @ (posedge vclk) beginvsync_reg <= vsync;hsync_reg <= hsync;vden_reg <= vden; endassign vsync_out = vsync_reg; assign hsync_out = hsync_reg; assign vden_out = vden_reg; /****Delay Signals************************/ endmodule

/* 求中值的中值。 */ `timescale 1ns/1psmodule mid_of_3(//inputvclk,vsync,hsync,vden,mid_x1,mid_x2,mid_x3,//outputvsync_out,hsync_out,vden_out,mid_of_mid ); input vclk; input vsync,hsync,vden; input [23:0] mid_x1,mid_x2,mid_x3; output [23:0] mid_of_mid; output vsync_out,hsync_out,vden_out;reg [23:0] mid_of_mid=24'h0; reg vsync_reg,hsync_reg,vden_reg;always@(posedge vclk) beginif(mid_x1<mid_x2)beginif(mid_x3<mid_x1)beginmid_of_mid<=mid_x1;endelse if(mid_x3<mid_x2)beginmid_of_mid<=mid_x3;endelsebeginmid_of_mid<=mid_x2;endend elsebeginif(mid_x3<mid_x2)beginmid_of_mid<=mid_x2;endelse if(mid_x3<mid_x1)beginmid_of_mid<=mid_x3;endelsebeginmid_of_mid<=mid_x1;endendend /****Delay Signals************************/ always @ (posedge vclk) beginvsync_reg <= vsync;hsync_reg <= hsync;vden_reg <= vden; endassign vsync_out = vsync_reg; assign hsync_out = hsync_reg; assign vden_out = vden_reg; /****Delay Signals************************/ endmodule
/*求最大值中的最小值。 */ `timescale 1ns/1psmodule min_of_3(//inputvclk,vsync,hsync,vden,max_x1,max_x2,max_x3,//outputvsync_out,hsync_out,vden_out,min_of_max ); input vclk; input vsync,hsync,vden; input [23:0] max_x1,max_x2,max_x3; output [23:0] min_of_max; output vsync_out,hsync_out,vden_out; reg [23:0] min_of_max=24'h0; reg vsync_reg,hsync_reg,vden_reg;always@(posedge vclk) beginif(max_x1<max_x2)beginif(max_x3<max_x1)beginmin_of_max<=max_x3;endelsebeginmin_of_max<=max_x1;endend elsebeginif(max_x3<max_x2)beginmin_of_max<=max_x3;endelse beginmin_of_max<=max_x2;endendend/****Delay Signals************************/ always @ (posedge vclk) beginvsync_reg <= vsync;hsync_reg <= hsync;vden_reg <= vden; endassign vsync_out = vsync_reg; assign hsync_out = hsync_reg; assign vden_out = vden_reg; /****Delay Signals************************/endmodule
/*求最大值中的最小值。 */ `timescale 1ns/1psmodule min_of_3(//inputvclk,vsync,hsync,vden,max_x1,max_x2,max_x3,//outputvsync_out,hsync_out,vden_out,min_of_max ); input vclk; input vsync,hsync,vden; input [23:0] max_x1,max_x2,max_x3; output [23:0] min_of_max; output vsync_out,hsync_out,vden_out; reg [23:0] min_of_max=24'h0; reg vsync_reg,hsync_reg,vden_reg;always@(posedge vclk) beginif(max_x1<max_x2)beginif(max_x3<max_x1)beginmin_of_max<=max_x3;endelsebeginmin_of_max<=max_x1;endend elsebeginif(max_x3<max_x2)beginmin_of_max<=max_x3;endelse beginmin_of_max<=max_x2;endendend/****Delay Signals************************/ always @ (posedge vclk) beginvsync_reg <= vsync;hsync_reg <= hsync;vden_reg <= vden; endassign vsync_out = vsync_reg; assign hsync_out = hsync_reg; assign vden_out = vden_reg; /****Delay Signals************************/endmodule
/* 求中值的中值。 */ `timescale 1ns/1psmodule mid_of_3(//inputvclk,vsync,hsync,vden,mid_x1,mid_x2,mid_x3,//outputvsync_out,hsync_out,vden_out,mid_of_mid ); input vclk; input vsync,hsync,vden; input [23:0] mid_x1,mid_x2,mid_x3; output [23:0] mid_of_mid; output vsync_out,hsync_out,vden_out;reg [23:0] mid_of_mid=24'h0; reg vsync_reg,hsync_reg,vden_reg;always@(posedge vclk) beginif(mid_x1<mid_x2)beginif(mid_x3<mid_x1)beginmid_of_mid<=mid_x1;endelse if(mid_x3<mid_x2)beginmid_of_mid<=mid_x3;endelsebeginmid_of_mid<=mid_x2;endend elsebeginif(mid_x3<mid_x2)beginmid_of_mid<=mid_x2;endelse if(mid_x3<mid_x1)beginmid_of_mid<=mid_x3;endelsebeginmid_of_mid<=mid_x1;endendend /****Delay Signals************************/ always @ (posedge vclk) beginvsync_reg <= vsync;hsync_reg <= hsync;vden_reg <= vden; endassign vsync_out = vsync_reg; assign hsync_out = hsync_reg; assign vden_out = vden_reg; /****Delay Signals************************/ endmodule
/*求最小值中的最大值。 */ `timescale 1ns/1psmodule max_of_3(//inputvclk,vsync,hsync,vden,min_x1,min_x2,min_x3,//outputvsync_out,hsync_out,vden_out,max_of_min ); input vclk; input vsync,hsync,vden; input [23:0] min_x1,min_x2,min_x3; output [23:0] max_of_min; output vsync_out,hsync_out,vden_out; reg [23:0] max_of_min=24'h0; reg vsync_reg,hsync_reg,vden_reg;always@(posedge vclk) beginif(min_x1>min_x2)beginif(min_x3>min_x1)beginmax_of_min<=min_x3;endelsebeginmax_of_min<=min_x1;endend elsebeginif(min_x3>min_x2)beginmax_of_min<=min_x3;endelse beginmax_of_min<=min_x2;endend end /****Delay Signals************************/ always @ (posedge vclk) beginvsync_reg <= vsync;hsync_reg <= hsync;vden_reg <= vden; endassign vsync_out = vsync_reg; assign hsync_out = hsync_reg; assign vden_out = vden_reg; /****Delay Signals************************/ endmodule
`timescale 1ns/1psmodule pro_final_of_mid(vsync,hsync,vden,vclk,vd11,vd12,vd13,vd21,vd22,vd23,vd31,vd32,vd33,vsync_out,hsync_out,vden_out,dout );input wire vsync; input wire hsync; input wire vden; input wire vclk; input wire [23:0] vd11; input wire [23:0] vd12; input wire [23:0] vd13; input wire [23:0] vd21; input wire [23:0] vd22; input wire [23:0] vd23; input wire [23:0] vd31; input wire [23:0] vd32; input wire [23:0] vd33; output wire vsync_out; output wire hsync_out; output wire vden_out; output wire [23:0] dout;wire [23:0] max_of_min; wire [23:0] max_x1; wire [23:0] max_x2; wire [23:0] max_x3; wire [23:0] mid_of_mid; wire [23:0] mid_x1; wire [23:0] mid_x2; wire [23:0] mid_x3; wire [23:0] min_of_max; wire [23:0] min_x1; wire [23:0] min_x2; wire [23:0] min_x3; wire [23:0] final_of_mid; wire vden1_out; wire vden11_out; wire vden12_out; wire vden2_out; wire vden21_out; wire vden22_out; wire vden3_out; wire hsync1_out; wire hsync11_out; wire hsync12_out; wire hsync2_out; wire hsync21_out; wire hsync22_out; wire hsync3_out; wire vsync1_out; wire vsync11_out; wire vsync12_out; wire vsync2_out; wire vsync21_out; wire vsync22_out; wire vsync3_out;reg [23:0] max_x1_reg; reg [23:0] max_x2_reg; reg [23:0] max_x3_reg; reg [23:0] mid_x1_reg; reg [23:0] mid_x2_reg; reg [23:0] mid_x3_reg; reg [23:0] min_x1_reg; reg [23:0] min_x2_reg; reg [23:0] min_x3_reg; reg [23:0] max_of_min_reg; reg [23:0] mid_of_mid_reg; reg [23:0] min_of_max_reg; reg vsync3_out_reg; reg hsync3_out_reg; reg vden3_out_reg; /****Cache Data******************************************/ always@(posedge vclk) beginvsync3_out_reg <= vsync3_out;hsync3_out_reg <= hsync3_out;vden3_out_reg <= vden3_out;min_x1_reg <= min_x1;mid_x1_reg <= mid_x1;max_x1_reg <= max_x1;min_x2_reg <= min_x2;mid_x2_reg <= mid_x2;max_x2_reg <= max_x2;min_x3_reg <= min_x3;mid_x3_reg <= mid_x3;max_x3_reg <= max_x3;max_of_min_reg <= max_of_min;mid_of_mid_reg <= mid_of_mid;min_of_max_reg <= min_of_max; end /****Cache Data******************************************/ rank_3_data rank_x1(.vclk(vclk),.vsync(vsync),.hsync(hsync),.vden(vden),.p1(vd31),.p2(vd21),.p3(vd11),.vsync_out(vsync1_out),.hsync_out(hsync1_out),.vden_out(vden1_out),.max(max_x1),.mid(mid_x1),.min(min_x1));rank_3_data rank_x2(.vclk(vclk),.vsync(vsync),.hsync(hsync),.vden(vden),.p1(vd32),.p2(vd22),.p3(vd12),.vsync_out(vsync11_out),.hsync_out(hsync11_out),.vden_out(vden11_out),.max(max_x2),.mid(mid_x2),.min(min_x2));rank_3_data rank_x3(.vclk(vclk),.vsync(vsync),.hsync(hsync),.vden(vden),.p1(vd33),.p2(vd23),.p3(vd13),.vsync_out(vsync12_out),.hsync_out(hsync12_out),.vden_out(vden12_out),.max(max_x3),.mid(mid_x3),.min(min_x3));max_of_3 pro_max_of_min(.vclk(vclk),.vsync(vsync1_out),.hsync(hsync1_out),.vden(vden1_out),.min_x1(min_x1),.min_x2(min_x2),.min_x3(min_x3),.vsync_out(vsync2_out),.hsync_out(hsync2_out),.vden_out(vden2_out),.max_of_min(max_of_min));mid_of_3 pro_mid_of_mid(.vclk(vclk),.vsync(vsync1_out),.hsync(hsync1_out),.vden(vden1_out),.mid_x1(mid_x1),.mid_x2(mid_x2),.mid_x3(mid_x3),.vsync_out(vsync21_out),.hsync_out(hsync21_out),.vden_out(vden21_out),.mid_of_mid(mid_of_mid));min_of_3 pro_min_of_max(.vclk(vclk),.vsync(vsync1_out),.hsync(hsync1_out),.vden(vden1_out),.max_x1(max_x1),.max_x2(max_x2),.max_x3(max_x3),.vsync_out(vsync22_out),.hsync_out(hsync22_out),.vden_out(vden22_out),.min_of_max(min_of_max));mid_of_3 pro_final_of_mid(.vclk(vclk),.vsync(vsync2_out),.hsync(hsync2_out),.vden(vden2_out),.mid_x1(max_of_min),.mid_x2(mid_of_mid),.mid_x3(min_of_max),.vsync_out(vsync3_out),.hsync_out(hsync3_out),.vden_out(vden3_out),.mid_of_mid(final_of_mid));assign vsync_out = vsync3_out_reg; assign hsync_out = hsync3_out_reg; assign vden_out = vden3_out_reg; assign dout = final_of_mid; endmodule
module pro_final_of_mid(//inputvclk,vsync,hsync,vden,vd11_in,vd12_in,vd13_in,vd21_in,vd22_in,vd23_in,vd31_in,vd32_in,vd33_in,//outputvsync_out,hsync_out,vden_out,final_of_mid,);/****Ports************************************/ input vclk; input vsync,hsync,vden; input [23:0] vd11_in,vd12_in,vd13_in,vd21_in,vd22_in,vd23_in,vd31_in,vd32_in,vd33_in; output [23:0] final_of_mid; output vsync_out,hsync_out,vden_out; /****Ports************************************//****Signals**********************************/ wire [23:0] vd11_in,vd12_in,vd13_in,vd21_in,vd22_in,vd23_in,vd31_in,vd32_in,vd33_in; wire [23:0] min_x1,mid_x1,max_x1; wire [23:0] min_x2,mid_x2,max_x2; wire [23:0] min_x3,mid_x3,max_x3; wire [23:0] max_of_min,mid_of_mid,min_of_max; reg [23:0] max_of_min_reg,mid_of_mid_reg,min_of_max_reg; wire [23:0] final_of_mid_reg; wire vsync,hsync,vden; wire vsync1_out,hsync1_out,vden1_out; wire vsync2_out,hsync2_out,vden2_out; wire vsync_out,hsync_out,vden_out; /****Signals**********************************/always@(posedge vclk) beginmax_of_min_reg<=max_of_min;mid_of_mid_reg<=mid_of_mid;min_of_max_reg<=min_of_max; endassign final_of_mid=final_of_mid_reg; //得出中值rank_3_data u1(.vclk(vclk),.vsyns(vsync),.hsync(hsync),.vden(vden),.p1(vd31_in),.p2(vd21_in),.p3(vd11_in),.vsyns_out(vsync1_out),.hsync_out(hsync1_out),.vden_out(vden1_out),.min(min_x1),.mid(mid_x1),.max(max_x1)); rank_3_data u2(.vclk(vclk),.vsyns(vsync),.hsync(hsync),.vden(vden),.p1(vd32_in),.p2(vd22_in),.p3(vd12_in),.vsyns_out(vsync1_out),.hsync_out(hsync1_out),.vden_out(vden1_out),.min(min_x2),.mid(mid_x2),.max(max_x2)); rank_3_data u3(.vclk(vclk),.vsyns(vsync),.hsync(hsync),.vden(vden),.p1(vd33_in),.p2(vd23_in),.p3(vd13_in),.vsyns_out(vsync1_out),.hsync_out(hsync1_out),.vden_out(vden1_out),.min(min_x3),.mid(mid_x3),.max(max_x3));//第1行排序 /*min_of_3 pro_max_of_min(.vclk(vclk),.vsyns(vsync1_out),.hsync(hsync1_out),.vden(vden1_out),.min_x1(min_x1),.min_x2(min_x2),.min_x3(min_x3),.vsyns_out(vsync2_out),.hsync_out(hsync2_out),.vden_out(vden2_out),.max_of_min(max_of_min)); //第2行排序 mid_of_3 pro_mid_of_mid(.vclk(vclk),.vsyns(vsync1_out),.hsync(hsync1_out),.vden(vden1_out),.mid_x1(mid_x1),.mid_x2(mid_x2),.mid_x3(mid_x3),.vsyns_out(vsync2_out),.hsync_out(hsync2_out),.vden_out(vden2_out),.mid_of_mid(mid_of_mid)); //第3行排序 max_of_3 pro_min_of_max(.vclk(vclk),.vsyns(vsync1_out),.hsync(hsync1_out),.vden(vden1_out),.max_x1(max_x1),.max_x2(max_x2),.max_x3(max_x3),.vsyns_out(vsync2_out),.hsync_out(hsync2_out),.vden_out(vden2_out),.min_of_max(min_of_max));//對角線排序 mid_of_3 pro_final_of_mid(.vclk(vclk),.vsyns(vsync2_out),.hsync(hsync2_out),.vden(vden2_out),.mid_x1(max_of_min_reg),.mid_x2(mid_of_mid_reg),.mid_x3(min_of_max_reg),.vsyns_out(vsync_out),.hsync_out(hsync_out),.vden_out(vden_out),.mid_of_mid(final_of_mid_reg)); */endmodule
/* 每一列三個數據的排序。插入排序法，最少比較2次，最多比較3次 */ `timescale 1ns/1psmodule rank_3_data(//inputvclk,vsync,hsync,vden,p1,p2,p3,//outputvsync_out,hsync_out,vden_out,min,mid,max ); input vclk; input vsync,hsync,vden; input [23:0] p1,p2,p3; output reg [23:0] min,mid,max; output vsync_out,hsync_out,vden_out; reg vsync_reg,hsync_reg,vden_reg;always @ (posedge vclk) beginif(p1<=p2)beginif(p3<=p1)beginmin<=p3;mid<=p1;max<=p2;endelse if(p3<=p2)beginmin<=p1;mid<=p3;max<=p2;endelsebeginmin<=p1;mid<=p2;max<=p3;endend elsebeginif(p3<=p2)beginmin<=p3;mid<=p2;max<=p1;endelse if(p3<=p1)beginmin<=p2;mid<=p3;max<=p1;endelsebeginmin<=p2;mid<=p1;max<=p3;endend end /****Delay Signals************************/ always @ (posedge vclk) beginvsync_reg <= vsync;hsync_reg <= hsync;vden_reg <= vden; endassign vsync_out = vsync_reg; assign hsync_out = hsync_reg; assign vden_out = vden_reg; /****Delay Signals************************/ endmodule
`timescale 1ns / 1psmodule shift_ram_256(//input:rst, //resetclk, //clocksen, //shift enabledin, //[23:0] data in//output:dout //[23:0] data out);/****Parameters*************************************************************/parameter DWIDTH = 24;parameter AWIDTH = 8;/****Parameters*************************************************************//****Port Definition********************************************************/input rst;input clk;input sen;input [DWIDTH-1:0] din;output [DWIDTH-1:0] dout;/****Port Definition********************************************************/ /****Signals****************************************************************/reg [DWIDTH-1:0] RAM [2**AWIDTH-1:0];reg [AWIDTH-1:0] wadr_reg;/****Signals****************************************************************//****Write******************************************************************/always @ (posedge clk)if(sen)RAM[wadr_reg] <= din;/****Write******************************************************************//****Read******************************************************************/assign dout = RAM[wadr_reg];/****Read******************************************************************//****Address***************************************************************/always @ (posedge clk)if(!rst)wadr_reg <= 8'd0;else if(sen)wadr_reg <= wadr_reg + 1'b1;/****Address***************************************************************/endmodule
`timescale 1ns / 1psmodule shifter(//input:input vclk,input vsync,input hsync,input vden,input [23:0] vd,//output:output vsync_out,output hsync_out,output vden_out,output [23:0] vd11_out,output [23:0] vd12_out,output [23:0] vd13_out,output [23:0] vd21_out,output [23:0] vd22_out,output [23:0] vd23_out,output [23:0] vd31_out,output [23:0] vd32_out,output [23:0] vd33_out);/****Parameters*****************************************************/parameter WIDTH = 8'd255;parameter HIGHT = 8'd255;parameter IDLE = 3'd0;parameter ADD1 = 3'd1;parameter ADD2 = 3'd2;parameter NORMAL1 = 3'd3;parameter NORMAL2 = 3'd4;parameter SUB = 3'd5;parameter ADD_VDEN = 3'd6;parameter WAIT = 3'd7;/****Parameters*****************************************************//****Signals Definition*********************************************/reg [2:0] state_reg;reg [15:0] cnt_reg;reg [7:0] row_reg;reg [7:0] col_reg;reg special_reg;reg vsync_reg;reg hsync_reg;reg vden_reg;reg vden2_reg;reg [23:0] vd_reg;wire [23:0] dout1;wire [23:0] dout2;wire vden_tmp;reg vsync_out_reg;reg hsync_out_reg;reg vden_out_reg;reg [23:0] vd21_out_reg;reg [23:0] vd22_out_reg;reg [23:0] vd23_out_reg;reg [23:0] vd31_out_reg;reg [23:0] vd32_out_reg;reg [23:0] vd33_out_reg;/****Signals Definition*********************************************//****Ctrl Signal Register*******************************************/always @ (posedge vclk)beginvsync_reg <= vsync;hsync_reg <= hsync;vden_reg <= vden;vd_reg <= vd;end/****Ctrl Signal Register*******************************************//****Vden Signal Delay**********************************************/always @ (posedge vclk)if(!vsync_reg)beginstate_reg <= IDLE; row_reg <= 8'd0;cnt_reg <= 16'd0;vden2_reg <= 1'b0;endelse begincase(state_reg)IDLE:beginif(vden_reg) state_reg <= ADD1;row_reg <= 8'd0;cnt_reg <= 16'd0;vden2_reg <= 1'b0;endADD1:beginif(!vden_reg)state_reg <= ADD2;cnt_reg <= cnt_reg + 1'b1;endADD2:beginif(vden_reg)state_reg <= NORMAL1;cnt_reg <= cnt_reg + 1'b1;vden2_reg <= vden; endNORMAL1:beginif(!vden_reg)state_reg <= NORMAL2;if(!vden_reg)row_reg <= row_reg + 1'b1;vden2_reg <= vden;endNORMAL2:beginif(vden_reg && row_reg == (HIGHT - 1'b1))state_reg <= SUB;else if(vden_reg)state_reg <= NORMAL1;vden2_reg <= vden;endSUB:beginif(cnt_reg == 16'd1)state_reg <= ADD_VDEN;if(!vden_reg)row_reg <= HIGHT;cnt_reg <= cnt_reg - 1'b1;vden2_reg <= vden;endADD_VDEN:beginif(cnt_reg == 16'd255)state_reg <= WAIT;cnt_reg <= cnt_reg + 1'b1;vden2_reg <= 1'b1;endWAIT:beginif(!vsync_reg)state_reg <= IDLE;vden2_reg <= 1'b0;enddefault:beginstate_reg <= IDLE; row_reg <= 8'd0;cnt_reg <= 16'd0;vden2_reg <= 1'b0;endendcaseend/****Vden Signal Delay**********************************************//****Two Shift RAM**************************************************/assign vden_tmp = vden_reg | vden2_reg;shift_ram_256 shift_ram_256_1(//input:.rst(vsync_reg), //reset.clk(vclk), //clock.sen(vden_tmp), //shift enable.din(dout2), //[23:0] data in//output:.dout(dout1) //[23:0] data out);shift_ram_256 shift_ram_256_2(//input:.rst(vsync_reg), //reset.clk(vclk), //clock.sen(vden_tmp), //shift enable.din(vd_reg), //[23:0] data in//output:.dout(dout2) //[23:0] data out);/****Two Shift RAM**************************************************//****Signal Output**************************************************/always @ (posedge vclk)if(vden2_reg)col_reg <= col_reg + 1'b1;elsecol_reg <= 8'd0;always @ (posedge vclk)beginvsync_out_reg <= vsync_reg;hsync_out_reg <= hsync_reg;vden_out_reg <= vden2_reg; endalways @ (posedge vclk)if(!vsync_reg)beginvd21_out_reg <= 24'd0;vd22_out_reg <= 24'd0;vd23_out_reg <= 24'd0;vd31_out_reg <= 24'd0;vd32_out_reg <= 24'd0;vd33_out_reg <= 24'd0;special_reg <= 1'b0;endelse if(vden2_reg)beginif(col_reg == 8'd0 || col_reg == WIDTH || row_reg == 8'd0 || row_reg == HIGHT)special_reg <= 1'b1;elsespecial_reg <= 1'b0;vd21_out_reg <= dout1;vd22_out_reg <= dout2;vd23_out_reg <= vd_reg;vd31_out_reg <= vd21_out_reg;vd32_out_reg <= vd22_out_reg;vd33_out_reg <= vd23_out_reg;end/****Signal Output**************************************************/ assign vsync_out = vsync_out_reg;assign hsync_out = hsync_out_reg;assign vden_out = vden_out_reg;assign vd11_out = special_reg ? vd22_out_reg : dout1;assign vd12_out = special_reg ? vd22_out_reg : dout2;assign vd13_out = special_reg ? vd22_out_reg : vd_reg;assign vd21_out = special_reg ? vd22_out_reg : vd21_out_reg;assign vd22_out = special_reg ? vd22_out_reg : vd22_out_reg;assign vd23_out = special_reg ? vd22_out_reg : vd23_out_reg;assign vd31_out = special_reg ? vd22_out_reg : vd31_out_reg;assign vd32_out = special_reg ? vd22_out_reg : vd32_out_reg;assign vd33_out = special_reg ? vd22_out_reg : vd33_out_reg;endmodule

matlab仿真涉及的文件：

A=imread('cameraman.tif'); imshow(A) B1=imnoise(A,'salt & pepper',0.02); t=change(B1); for c11=1:2:241 for c12=1:2:307 xl=number(c11,cl2,t); if(selfmax(c11,cl2,t)-selfmin(cl1,c12,t))>2O&xl>0 [q11,q12]=noise(c11,cl2,t); t(q11,q12)=selfmin(cl1,cl2,t); end if(selfmax(cl1,c12,t)-selfmin(cl1,c12,t))<2O&xl>0 [q11,ql2]=noise(c11,c12,1); t(ql1,ql2)=meanfilter(cl1,cl2,t); end end end imshow(t)
A=imread('cameraman.tif'); imshow(A) B1=imnoise(A,'salt & pepper',0.02); t=change(B1); for c11=1:2:241 for c12=1:2:307 xl=number(c11,cl2,t); if(selfmax(c11,cl2,t)-selfmin(cl1,c12,t))>2O&xl>0 [q11,q12]=noise(c11,cl2,t); t(q11,q12)=selfmin(cl1,cl2,t); end if(selfmax(cl1,c12,t)-selfmin(cl1,c12,t))<2O&xl>0 [q11,ql2]=noise(c11,c12,1); t(ql1,ql2)=meanfilter(cl1,cl2,t); end end end imshow(t)
clear all; close all;%----Load Image----------------------------------------------------------- img = imread('cameraman_zaodian.jpg'); %If you want test other picture,%change it's name here. imshow(img); %Show the selectted image. %----Load Image----------------------------------------------------------- %----Write Image Data In RAM Format--------------------------------------- file = fopen('img_cameraman_zaodian_x.txt', 'w'); %Hex Format Data, used to inital%The RAM in modelsim. R = uint8(0); G = uint8(0); B = uint8(0) for row = 1:256for col = 1:256R = uint8(img(row,col,1));G = uint8(img(row,col,2));B = uint8(img(row,col,3));if(R < 16)fprintf(file,'0');endfprintf(file,'%x',R);if(G < 16)fprintf(file,'0');endfprintf(file,'%x',G);if(B < 16)fprintf(file,'0');endfprintf(file,'%x\n',B);end end %----Write Image Data In RAM Format---------------------------------------
clear all clear all I=imread('cameraman.jpg');%讀入原圖像 J=imread('cameraman_zaodian.jpg');%讀入已含有噪點的圖像 %---顯示 原圖像，已含有噪點的圖像------------------------------------------ subplot(131),imshow(I) title('原圖像') subplot(132),imshow(J) title('噪點圖像')%---顯示 原圖像，已含有噪點的圖像-------------------------------------------%---將 噪點圖像 經過 噪點處理（FPGA）后，顯示--------------------------------%----Data loading---------------------------------------------------------- data_fpga = load('fpga_cameraman_zaodian.txt'); %----Data loading----------------------------------------------------------%---- median_filter_fpga-------------------------------------------------- img_median_filter_fpga = uint8(zeros(256,256,3)); for row = 1:256for col =1:256img_median_filter_fpga(row,col,1) = data_fpga((row-1)*256*3 + (col-1)*3 + 1);img_median_filter_fpga(row,col,2) = data_fpga((row-1)*256*3 + (col-1)*3 + 2);img_median_filter_fpga(row,col,3) = data_fpga((row-1)*256*3 + (col-1)*3 + 3);end end subplot(1,3,3); imshow(img_median_filter_fpga); title('中值濾波 fpga '); %---- median_filter_fpga----------------------------------------------------%---將 噪點圖像 經過 噪點處理（FPGA）后，顯示----------------------------------------

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