最近嘗試了很多方法測(cè)量占空比，雖然說原理簡(jiǎn)單，但是測(cè)量的時(shí)候誤差還是挺大的，凡是沒呢么容易，

最后終于實(shí)現(xiàn)了1HZ-5M 占空比的測(cè)量，精度小于%0.1

另外發(fā)現(xiàn)了一個(gè)問題，fpga一條語句如果很復(fù)雜的話，可能會(huì)出現(xiàn)問題。

例如 assign ?duty_altera = pinlv << 1 + pinlv;也就是pinlv_altera 是頻率的三倍，在sigtab仿真時(shí)出錯(cuò)了，如果把這兩條語句分開寫就沒毛病了。

這說明在200M高速頻率下，這樣寫法不太好，跑不了高速。

程序思路：

設(shè)定一個(gè)1S鐘的閘門，在閘門有效期間測(cè)量高電平持續(xù)時(shí)間和低電平持續(xù)時(shí)間，需要注意的是：

在測(cè)量時(shí)間時(shí)需要以邊沿做為開始計(jì)數(shù)的標(biāo)志，否則程序容易崩潰。然而實(shí)際測(cè)量出來，還是有誤差的，經(jīng)過測(cè)量多組數(shù)據(jù)發(fā)現(xiàn)：高電平測(cè)量的時(shí)間所記錄的個(gè)數(shù)比實(shí)際上少記錄了2*pinlv個(gè)，而低電平恰恰相反。經(jīng)過補(bǔ)償，滿足題目的要求。

module duty(//system interfaceinput clk,input rst_n,//sig interfaceinput sig_in,//pinlv interfaceinput [31:0] pinlv,//user interfaceoutput reg [15:0] duty,output reg [31:0] cnt_high,output reg [31:0] cnt_low,output high_pulse,output low_pulse,output [31:0] duty_alter );//buffer reg sig_in_buffer; reg sig_in_buffer1; always @(posedge clk or negedge rst_n) beginif(!rst_n)beginsig_in_buffer <= 0;sig_in_buffer1 <= 0;endelsebeginsig_in_buffer <= sig_in;sig_in_buffer1 <= sig_in_buffer;end end assign high_pulse = (sig_in_buffer == 1 && sig_in_buffer1 == 0) ? 1 : 0; assign low_pulse = (sig_in_buffer == 0 && sig_in_buffer1 == 1) ? 1 : 0; //parameter CNT_1S = 32'd199_9; parameter CNT_1S = 32'd199_999_999; reg [31:0] cnt_1s; reg fgate;always @(posedge clk or negedge rst_n) beginif(!rst_n)cnt_1s <= 0;else if(cnt_1s >= CNT_1S)cnt_1s <= 0;else cnt_1s <= cnt_1s + 1; endalways @(posedge clk or negedge rst_n) beginif(!rst_n)fgate <= 0;else if(cnt_1s == CNT_1S)fgate <= ~fgate;elsefgate <= fgate; endreg fstart; always @(posedge sig_in_buffer1 or negedge rst_n) beginif(!rst_n)fstart <= 0;else if(fgate)fstart <= 1;elsefstart <= 0; end reg [2:0] state_high; reg [2:0] state_low; //cnt reg [31:0] cnt_high_temp; reg [31:0] cnt_low_temp;always @(posedge clk or negedge rst_n) beginif(!rst_n)state_high <= 0;elsecase(state_high)2'd0 :beginif(high_pulse)state_high <= 2'd1;elsestate_high <= 2'd0;end2'd1 :beginif(low_pulse)state_high <= 2'd0;elsestate_high <= 2'd1;enddefault : ;endcase endalways @(posedge clk or negedge rst_n) beginif(!rst_n)state_low <= 0;elsecase(state_low)2'd0 :beginif(low_pulse)state_low <= 2'd1;elsestate_low <= 2'd0;end2'd1 :beginif(high_pulse)state_low <= 2'd0;elsestate_low <= 2'd1;enddefault : ;endcase end always @(posedge clk or negedge rst_n) beginif(!rst_n)cnt_high_temp <= 0;else if(fstart)beginif(state_high == 1)cnt_high_temp <= cnt_high_temp + 1;elsecnt_high_temp <= cnt_high_temp;endelsecnt_high_temp <= 0; endalways @(posedge clk or negedge rst_n) beginif(!rst_n)cnt_low_temp <= 0;else if(fstart)beginif(state_low == 1)cnt_low_temp <= cnt_low_temp + 1;elsecnt_low_temp <= cnt_low_temp;endelsecnt_low_temp <= 0; end wire [31:0] pinlv1; assign pinlv1 = pinlv << 1; assign duty_alter = pinlv << 1;always @(negedge fstart or negedge rst_n) beginif(!rst_n)begincnt_high <= 0;cnt_low <= 0;endelsebegincnt_high <= cnt_high_temp + duty_alter ;cnt_low <= cnt_low_temp - duty_alter ; end endendmodule

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轉(zhuǎn)載于:https://www.cnblogs.com/bixiaopengblog/p/6915653.html

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