兩段式狀態機不可能完成的任務（特權）

???????? 最近折騰狀態機，發現一個小任務對于兩段式狀態機寫法是不可能完成的。這個小任務很簡單，先看用一段式狀態機實現的代碼：

module test(

??????????? clk,rst_n,

??????????? din,dout

??????? );

?

input clk;

input rst_n;???

input din;

output[3:0] dout;??

?

parameter IDLE? = 3'd0;

parameter STA1? = 3'd1;

?

//一段式寫法

reg[2:0] cstate;

reg[3:0] cnt;

?

always @(posedge clk or negedge rst_n)

??? if(!rst_n) cstate <= IDLE;

??? else begin

??????? case(cstate)

??????????? IDLE: begin

??????????????????? cnt <= 4'd0;

??????????????????? if(din) cstate <= STA1;

??????????????????? else cstate <= IDLE;???????

??????????????? end

??????????? STA1: begin

??????????????????? cnt <= cnt+1'b1;

??????????????????? if(cnt == 4'd10) cstate <= IDLE;

??????????????????? else cstate <= STA1;

??????????????? end

??????????? default: cstate <= IDLE;

??????? endcase

??? end

?

assign dout = cnt;

?

endmodule

???????? 同樣的，用三段式狀態機也能夠實現這個功能：

//三段式寫法

reg[2:0] cstate,nstate;

reg[3:0] cnt;

?

always @(posedge clk or negedge rst_n)

??? if(!rst_n) cstate <= IDLE;

??? else cstate <= nstate;

?

always @(cstate or din or cnt) begin

??? case(cstate)

??????? IDLE: ? if(din) nstate = STA1;

??????????????? else nstate = IDLE;????

??????? STA1: ? if(cnt == 4'd10) nstate = IDLE;

??????????????? else nstate = STA1;

??????? default: nstate = IDLE;

??? endcase

end

?

always @(posedge clk or negedge rst_n)

??? if(!rst_n) cnt <= 4'd0;

??? else begin

??????? case(nstate)

??????????? IDLE: ? cnt <= 4'd0;

??????????? STA1: ? cnt <= cnt+1'b1;

??????????? default: ;

??????? endcase

??? end

???????? 嚴格來看，上面的三段式狀態機相比于一段式會滯后一個時鐘周期。但是我們的重點不在這里，大家大可以不必鉆這個牛角尖。另外，這個實例實現的功能本身也沒 有什么意義，當然也是可以用別的更簡單（不需要狀態機）的方式實現，但是你可以想象成這是實際應用中狀態機各種復雜輸出的一部分。

???????? 而如果大家希望用兩段式狀態機實現這個功能，或許會這么寫：

//兩段式寫法

reg[2:0] cstate,nstate;

reg[3:0] cnt;

?

always @(posedge clk or negedge rst_n)

??? if(!rst_n) cstate <= IDLE;

??? else cstate <= nstate;

?

always @(cstate or din or cnt) begin

??? case(cstate)

??????? IDLE: begin

??????????????? cnt = 4'd0;

??????????????? if(din) nstate = STA1;

??????????????? else nstate = IDLE;????

??????????? end

??????? STA1: begin

??????????????? cnt = cnt+1'b1;

??????????????? if(cnt == 4'd10) nstate = IDLE;

??????????????? else nstate = STA1;

??????? ??? end

??????? default: nstate = IDLE;

??? endcase

end

???????? 如果大家有興趣對三中代碼方式都做一下仿真，會發現一些有意思的問題，尤其兩段式狀態機最終根本無法退出STA1，計數器cnt也會死在那里。究其根本原因，可大有學問。在編譯工程后，出現了數條類似下面的warning：

Warning: Found combinational loop of 2 nodes

??? Warning: Node "Add0~2"

??? Warning: Node "cnt~9"

??????? 何為combinational loop？讓handbook來解釋吧，看不懂英文的可別怪我~_~

Combinational loops are among the most common causes of instability and unreliability in digital designs. They should be avoided whenever possible. In a synchronous design, feedback loops should include registers. Combinational loops generally violate synchronous design principles by establishing a direct feedback loop that contains no registers. For example, a combinational loop occurs when the left-hand side of an arithmetic expression also appears on the right-hand side in HDL code. A combinational loop also occurs when you feed back the output of a register to an asynchronous pin of the same register through combinational logic, as shown in Figure 5–1.

? ? ? ? 沒有寄存器打一拍的這種combinational loop（組合環）是一種不推薦的設計方式，就如兩段式狀態機所實現的效果，甚至最終無法實現功能要求。同樣的功能，一段式和三段式狀態機之所以能夠解決 這個問題，就是避免了在純組合邏輯中涉及這個反饋邏輯。在初學verilog時，我們常提的latch（鎖存器），其實也是combinational loop的一個特例。

轉載于:https://www.cnblogs.com/lueguo/p/3582250.html

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