1、硬件連接

當系統復位后, s3c44b0x從0x00000000地址處讀取指令。并且s3c44b0x在復位后必須進行系統參數配置。
因此這段特殊代碼(BOOT ROM鏡像)必須位于地址0x00000000, boot ROM的數據總線寬度可以通過OM[1:0]引腳進行配置。
表1.1、ROM Bank 0數據總線寬度

OM[1:0]	數據總線寬度
00	8-bit(byte)
01	16-bit(half-word)
10	32-bit(word)
11	測試模式

s3c44b0x開發板上使用的BOOT ROM芯片為：Am29LV160DB-90 (16 Megabit (2 M x 8-Bit/1 M x 16-Bit))

圖1.1、使用HALF-WORD EEPROM/FLASH進行HALF-WORD BOOT ROM設計參考：

圖2.1、s3c44b0x開發板Am29LV160DB-90實際電路

注：此處2.0R5是用于容量擴展, 實際電路板上并無此電阻

2、軟件初始化

參考s3c44b0x用戶指南可知, 與BOOT ROM相關的寄存器有:
(1)、總線寬度與等待控制寄存器(BWSCON)
(2)、BANK控制寄存器(BANKCON0: nGCS0)

表2.1、BWSCON與BOOT ROM相關的選項為:

BWSCON	Bit	描述	起始狀態
DW0	[2:1]	指示bank 0的數據總線寬度(只讀) 00 = 8-bit, 01 = 16-bit, 10 = 32bit 通過OM[1:0]引腳進行選擇	-
ENDIAN	[0]	指示bank 0的endian模式(只讀) 0 = Little endian, 1 = Big endian 通過ENDIAN引腳進行選擇	-

表2.2、BANKCON0

BANKCON0	Bit	描述	起始狀態
Tacs	[14:13]	Address set-up before nGCSn 00 = 0 clock, 01 = 1 clock 10 = 2 clocks, 11 = 4 clocks	00
Tcos	[12:11]	Chip selection set-up nOE 00 = 0 clock, 01 = 1 clock 10 = 2 clocks, 11 = 4 clocks	00
Tacc	[10:8]	Access cycle 000 = 1 clock, 001 = 2 clocks 010 = 3 clocks, 011 = 4 clocks 100 = 6 clocks, 101 = 8 clocks 110 = 10 clocks, 111 = 14 clocks	111
Toch	[7:6]	Chip selection hold on nOE 00 = 0 clock, 01 = 1 clock 10 = 2 clocks, 11 = 4 clocks	00
Tcah	[5:4]	Address holding time after nGCSn 00 = 0 clock, 01 = 1 clock 10 = 2 clocks, 11 = 4 clocks	00
Tpac	[3:2]	Page mode access cycle @ Page mode 00 = 2 clocks, 01 = 3 clocks 10 = 4 clocks, 11 = 6 clocks	00
PMC	[1:0]	Page mode configuration 00 = normal (1 data), 01 = 4 data 10 = 8 data, 11 = 16 data	00

注: All types of master clock in this memory controller correspond to the bus clock.
???? 所有此存儲器控制器主機時鐘的類型與總線時鐘相符.
???? For example, MCLK in DRAM and SRAM is same as the bus clock, and SCLK in SDRAM is also the same as the bus
???? clock. In this chapter (Memory Controller), one clock means one bus clock.
???? 例如, DRAM和SRAM中的MCLK與總線時鐘相同, 并且SDRAM的SCLK也與總線時鐘相同, 在這章中(存儲器控制器), 1個時鐘是指一個總線時鐘.

其中: 由于Am29LV160DB-90不支持Page Mode(Am29PL160C支持Page Mode), Tpac和PMC對于BOOT ROM不需要進行設置,
需要進行設置的值有: Tacs, Tcos, Tacc, Toch, Tcah.
圖2.1 s3c44b0x ROM/SRAM 讀時序 (I) (Tacs=2,Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0)

注：對于bank 0, ST不可設置, ST = 0

圖2.2 Am29LV160DB-90讀操作時序

根據圖2.1和圖2.2可知:

s3c44b0x	Am29LV160DB-90
Tacs + tRCD – tRAD	tACC – tCE
Tcos - tRCD + tROD	tCE - tOE
Tacc - tROD + tROD	tRC - tACC + tOE
Toch	0
Tcah	0

通過查看s3c44b0x和Am29LV160D數據手冊, 可知:
s3c44b0x: tRCD = 11ns, tRAD = 12ns, tROD = 11ns
Am29LV160D: tACC = 90ns, tCE = 90ns. tOE = 35ns, tRC = 90ns
因此Tacs = 1ns, Tcos = 55ns, Tacc = 35ns, Toch = 0ns, Tcah = 0ns
假設系統總線時鐘為60MHz, one clock = 1 / (60MHz) = (50 / 3)ns
Tacs = 1ns = 1 / (50 / 3) clock = 0.06 clock = 0 clock
Tcos = 55ns = 55 / (50 / 3) clock = 3.3 clock = 4 clocks
Tacc = 35ns = 35 / (50 / 3) clock = 2.1 clock = 3 clocks
Toch = 0ns = 0 clock
Tcah = 0ns= 0 clock
BANKCON0 = 0b 00 11 010 00 00 00 00 = 0x00001a00
到此s3c44b0x BOOT ROM配置完成

轉載于:https://www.cnblogs.com/arci/archive/2011/04/17/2018955.html

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