該補丁實現的功能如下：

1.支持norflash，成功識別，并無測試讀寫(讀者可自行測試)；

2.從nandflash啟動，實現自拷貝；

3.支持dm9000網卡，并增加TFTP界面方便下載；

4.支持yaffs文件系統的下載(手動下載請自行跳過第一個好塊，暫時沒時間修改代碼)；

5.支持開機畫面和LCD控制臺(雞肋功能)。

6.啟動界面如下：

U-Boot 2012.07 (Oct 19 2012 - 17:04:34)FCLK: 200 MHz HCLK: 100 MHz PCLK: 50 MHz DRAM: 64 MiB Flash: 4 MiB NAND: 256 MiB Video: 320x240x16 14kHz 53Hz Net: dm9000 Hit any key to stop autoboot: 0 ##### tftp menu for SMDK2440 ##### [1] Download u-boot.bin to Nand Flash [2] Download uImage to Nand Flash [3] Download root_yaffs2to Nand Flash [4] Download u-boot.bin to SDRAM &Run [5] Download uImage to SDRAM &Run [b] Boot the system [r] Reboot u-boot [q] Quit from menu Enter your selection: q SMDK2440#

uboot的最新版本的移植要注意如下幾點：

1.uboot的自拷貝分為兩階段。

第一階段拷貝到指定的SDRAM地址(鏈接地址)，這部分是需要自己實現的；

這里要注意的是要把自拷貝代碼放在nandflash的前4k中，方法是修改u-boot.lds。

.text :{__image_copy_start = .;CPUDIR/start.o (.text)board/samsung/smdk2440/libsmdk2440.o (.text)*(.text)}

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第二階段拷貝到uboot自己計算得出的地址，這部分是不需要做任何修改的。

2.修改配置文件位置是./boards.cfg。

smdk2410 arm arm920t - samsung s3c24x0 smdk2440 arm arm920t - samsung s3c24x0

3.修改交叉編譯鏈的位置是./arch/arm/config.mk。

#CROSS_COMPILE ?= arm-linux- CROSS_COMPILE ?= arm-unknown-linux-gnueabi-

4.修改鏈接地址的位置是include/configs/smdk2440.h。

#define CONFIG_SYS_TEXT_BASE 0x31000000 #define CONFIG_SYS_LDSCRIPT "board/samsung/smdk2440/u-boot.lds"

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補丁使用方式：

cd u-boot-2012.07 patch -p1 < [補丁絕對地址] make smdk2440_config make

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u-boot-2012.07_fl2440.patch：

View Code diff -uNr u-boot-2012.07/arch/arm/config.mk u-boot-2012.07_fl2440/arch/arm/config.mk --- u-boot-2012.07/arch/arm/config.mk 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/arch/arm/config.mk 2012-10-02 12:45:32.000000000 +0800 @@ -21,7 +21,8 @@# MA 02111-1307 USA#-CROSS_COMPILE ?= arm-linux- +#CROSS_COMPILE ?= arm-linux- +CROSS_COMPILE ?= arm-unknown-linux-gnueabi-ifndef CONFIG_STANDALONE_LOAD_ADDRifeq ($(SOC),omap3) diff -uNr u-boot-2012.07/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c u-boot-2012.07_fl2440/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c --- u-boot-2012.07/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c 2012-10-02 20:44:16.000000000 +0800 @@ -45,10 +45,10 @@struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();cpuid = readl(&gpio->gstatus1); - printf("CPUID: %8lX\n", cpuid); + debug("CPUID: %8lX\n", cpuid);#endiffor (i = 0; i < ARRAY_SIZE(freq_f); i++) - printf("%cCLK: %8s MHz\n", freq_c[i], strmhz(buf, freq_f[i]())); + printf("%cCLK: %4s MHz\n", freq_c[i], strmhz(buf, freq_f[i]()));return 0;} diff -uNr u-boot-2012.07/arch/arm/cpu/arm920t/start.S u-boot-2012.07_fl2440/arch/arm/cpu/arm920t/start.S --- u-boot-2012.07/arch/arm/cpu/arm920t/start.S 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/arch/arm/cpu/arm920t/start.S 2012-10-10 22:42:37.000000000 +0800 @@ -161,17 +161,19 @@mov r1, #0xffffffffldr r0, =INTMSKstr r1, [r0] -# if defined(CONFIG_S3C2410) +# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)ldr r1, =0x3ffldr r0, =INTSUBMSKstr r1, [r0]# endif+#if 0/* FCLK:HCLK:PCLK = 1:2:4 *//* default FCLK is 120 MHz ! */ldr r0, =CLKDIVNmov r1, #3str r1, [r0] +#endif#endif /* CONFIG_S3C24X0 *//* @@ -182,6 +184,20 @@bl cpu_init_crit#endif+#ifdef CONFIG_S3C2440 + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + bl clock_init +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, =(CONFIG_SYS_TEXT_BASE) /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq call_board_init_f + + ldr r2, _end_ofs + bl CopyCode2Ram /* r0: source, r1: dest, r2: size */ + ldr pc, =call_board_init_f +#endif +/* Set stackpointer in internal RAM to call board_init_f */call_board_init_f:ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) @@ -278,9 +294,11 @@b clbss_lclbss_e:+#ifndef CONFIG_S3C2440bl coloured_LED_initbl red_led_on#endif +#endif/** We are done. Do not return, instead branch to second part of board diff -uNr u-boot-2012.07/arch/arm/include/asm/mach-types.h u-boot-2012.07_fl2440/arch/arm/include/asm/mach-types.h --- u-boot-2012.07/arch/arm/include/asm/mach-types.h 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/arch/arm/include/asm/mach-types.h 2012-10-19 17:04:26.000000000 +0800 @@ -14222,6 +14222,18 @@# define machine_is_omap5_sevm() (0)#endif+#ifdef CONFIG_ARCH_SMDK2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2440 +# endif +# define machine_is_smdk2440() (machine_arch_type == MACH_TYPE_SMDK2440) +#else +# define machine_is_smdk2440() (0) +#endif +/** These have not yet been registered*/ diff -uNr u-boot-2012.07/arch/arm/lib/board.c u-boot-2012.07_fl2440/arch/arm/lib/board.c --- u-boot-2012.07/arch/arm/lib/board.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/arch/arm/lib/board.c 2012-10-04 14:37:21.000000000 +0800 @@ -566,14 +566,12 @@#endifstdio_init(); /* get the devices list going. */ -jumptable_init();#if defined(CONFIG_API)/* Initialize API */api_init();#endif -console_init_r(); /* fully init console as a device */#if defined(CONFIG_ARCH_MISC_INIT) diff -uNr u-boot-2012.07/arch/arm/lib/cache.c u-boot-2012.07_fl2440/arch/arm/lib/cache.c --- u-boot-2012.07/arch/arm/lib/cache.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/arch/arm/lib/cache.c 2012-10-02 20:27:40.000000000 +0800 @@ -61,7 +61,7 @@*/void __enable_caches(void){ - puts("WARNING: Caches not enabled\n"); + debug("WARNING: Caches not enabled\n");}void enable_caches(void)__attribute__((weak, alias("__enable_caches"))); diff -uNr u-boot-2012.07/board/samsung/smdk2440/clock.c u-boot-2012.07_fl2440/board/samsung/smdk2440/clock.c --- u-boot-2012.07/board/samsung/smdk2440/clock.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2012.07_fl2440/board/samsung/smdk2440/clock.c 2012-10-03 23:40:31.000000000 +0800 @@ -0,0 +1,49 @@ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h> + +#define S3C2440_MPLL_400MHZ ((0x5c<<12)|(0x01<<4)|(0x01)) +#define S3C2440_MPLL_200MHZ ((0x5c<<12)|(0x01<<4)|(0x02)) +#define S3C2440_MPLL_100MHZ ((0x5c<<12)|(0x01<<4)|(0x03)) +#define S3C2440_UPLL_96MHZ ((0x38<<12)|(0x02<<4)|(0x01)) +#define S3C2440_UPLL_48MHZ ((0x38<<12)|(0x02<<4)|(0x02)) +#define S3C2440_CLKDIV148 (0x05) /* FCLK:HCLK:PCLK = 1:4:8, UCLK = UPLL */ +#define S3C2440_CLKDIV124 (0x03) /* FCLK:HCLK:PCLK = 1:2:4, UCLK = UPLL */ + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + + +void clock_init(void) +{ + struct s3c24x0_clock_power *clk_power = (struct s3c24x0_clock_power *)0x4C000000; + + /* FCLK:HCLK:PCLK = 1:4:8 */ + clk_power->clkdivn = S3C2440_CLKDIV124; + + /* change to asynchronous bus mod */ + __asm__( "mrc p15, 0, r1, c1, c0, 0\n" /* read ctrl register */ + "orr r1, r1, #0xc0000000\n" /* Asynchronous */ + "mcr p15, 0, r1, c1, c0, 0\n" /* write ctrl register */ + :::"r1" + ); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + clk_power->locktime = 0xFFFFFFFF; + + /* configure UPLL */ + clk_power->upllcon = S3C2440_UPLL_48MHZ; + + /* some delay between MPLL and UPLL */ + delay (4000); + + /* configure MPLL */ + clk_power->mpllcon = S3C2440_MPLL_200MHZ; + + /* some delay between MPLL and UPLL */ + delay (8000); +} diff -uNr u-boot-2012.07/board/samsung/smdk2440/lowlevel_init.S u-boot-2012.07_fl2440/board/samsung/smdk2440/lowlevel_init.S --- u-boot-2012.07/board/samsung/smdk2440/lowlevel_init.S 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2012.07_fl2440/board/samsung/smdk2440/lowlevel_init.S 2012-10-02 09:42:49.000000000 +0800 @@ -0,0 +1,167 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + + +/* some parameters for the board */ + +/* + * + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S + * + * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com> + * + */ + +#define BWSCON 0x48000000 + +/* BWSCON */ +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) + +#define B1_BWSCON (DW16) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + UBLB) +#define B4_BWSCON (DW16 + WAIT + UBLB) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) + +/* BANK0CON */ +#define B0_Tacs 0x0 /* 0clk */ +#define B0_Tcos 0x0 /* 0clk */ +#define B0_Tacc 0x7 /* 14clk */ +#define B0_Tcoh 0x0 /* 0clk */ +#define B0_Tah 0x0 /* 0clk */ +#define B0_Tacp 0x0 +#define B0_PMC 0x0 /* normal */ + +/* BANK1CON */ +#define B1_Tacs 0x0 /* 0clk */ +#define B1_Tcos 0x0 /* 0clk */ +#define B1_Tacc 0x7 /* 14clk */ +#define B1_Tcoh 0x0 /* 0clk */ +#define B1_Tah 0x0 /* 0clk */ +#define B1_Tacp 0x0 +#define B1_PMC 0x0 + +#define B2_Tacs 0x0 +#define B2_Tcos 0x0 +#define B2_Tacc 0x7 +#define B2_Tcoh 0x0 +#define B2_Tah 0x0 +#define B2_Tacp 0x0 +#define B2_PMC 0x0 + +#define B3_Tacs 0x0 /* 0clk */ +#define B3_Tcos 0x3 /* 4clk */ +#define B3_Tacc 0x7 /* 14clk */ +#define B3_Tcoh 0x1 /* 1clk */ +#define B3_Tah 0x0 /* 0clk */ +#define B3_Tacp 0x3 /* 6clk */ +#define B3_PMC 0x0 /* normal */ + +#define B4_Tacs 0x0 /* 0clk */ +#define B4_Tcos 0x0 /* 0clk */ +#define B4_Tacc 0x7 /* 14clk */ +#define B4_Tcoh 0x0 /* 0clk */ +#define B4_Tah 0x0 /* 0clk */ +#define B4_Tacp 0x0 +#define B4_PMC 0x0 /* normal */ + +#define B5_Tacs 0x0 /* 0clk */ +#define B5_Tcos 0x0 /* 0clk */ +#define B5_Tacc 0x7 /* 14clk */ +#define B5_Tcoh 0x0 /* 0clk */ +#define B5_Tah 0x0 /* 0clk */ +#define B5_Tacp 0x0 +#define B5_PMC 0x0 /* normal */ + +#define B6_MT 0x3 /* SDRAM */ +#define B6_Trcd 0x1 +#define B6_SCAN 0x1 /* 9bit */ + +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x1 /* 3clk */ +#define B7_SCAN 0x1 /* 9bit */ + +/* REFRESH parameter */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define Trp 0x0 /* 2clk */ +#define Trc 0x3 /* 7clk */ +#define Tchr 0x2 /* 3clk */ +#define REFCNT 0x4f4 /* period=7.8125us, HCLK=100Mhz, (2048+1-7.8125*100) */ +/**************************************/ + +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #13*4 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +SMRDATA: + .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) + .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) + .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) + .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) + .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) + .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) + .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) + .word 0x81 + .word 0x30 + .word 0x30 diff -uNr u-boot-2012.07/board/samsung/smdk2440/Makefile u-boot-2012.07_fl2440/board/samsung/smdk2440/Makefile --- u-boot-2012.07/board/samsung/smdk2440/Makefile 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2012.07_fl2440/board/samsung/smdk2440/Makefile 2012-10-01 14:03:55.000000000 +0800 @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := smdk2440.o clock.o nandflash.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -uNr u-boot-2012.07/board/samsung/smdk2440/nandflash.c u-boot-2012.07_fl2440/board/samsung/smdk2440/nandflash.c --- u-boot-2012.07/board/samsung/smdk2440/nandflash.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2012.07_fl2440/board/samsung/smdk2440/nandflash.c 2012-10-06 10:06:20.000000000 +0800 @@ -0,0 +1,301 @@ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h> + +#define BUSY 1 +#define NAND_SECTOR_SIZE 512 +#define NAND_BLOCK_MASK (NAND_SECTOR_SIZE - 1) +#define NAND_SECTOR_SIZE_LP 2048 +#define NAND_BLOCK_MASK_LP (NAND_SECTOR_SIZE_LP - 1) +#define NAND_PAGE_SIZE_LP 64 +#define NAND_PAGE_MASK_LP (NAND_PAGE_SIZE_LP - 1) + +#define TACLS 0 +#define TWRPH0 3 +#define TWRPH1 0 + +/* NAND Flash操作的總入口, 它們將調用S3C2440的相應函數 */ +static void nand_reset(void); +static void wait_idle(void); +static void nand_select_chip(void); +static void nand_deselect_chip(void); +static void write_cmd(int cmd); +static void write_addr_lp(unsigned int addr); +static unsigned char read_data(void); + +/* S3C2440的NAND Flash處理函數 */ +static void s3c2440_nand_reset(void); +static void s3c2440_wait_idle(void); +static void s3c2440_nand_select_chip(void); +static void s3c2440_nand_deselect_chip(void); +static void s3c2440_write_cmd(int cmd); +static void s3c2440_write_addr_lp(unsigned int addr); +static unsigned char s3c2440_read_data(void); + +/* S3C2440的NAND Flash操作函數 */ + +/* 復位 */ +static void s3c2440_nand_reset(void) +{ + s3c2440_nand_select_chip(); + s3c2440_write_cmd(0xff); // 復位命令 + s3c2440_wait_idle(); + s3c2440_nand_deselect_chip(); +} + +/* 等待NAND Flash就緒 */ +static void s3c2440_wait_idle(void) +{ + int i; + struct s3c2440_nand * s3c2440nand = (struct s3c2440_nand *)0x4e000000; + volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->nfstat; + + while(!(*p & BUSY)) + for(i=0; i<10; i++); +} + +/* 發出片選信號 */ +static void s3c2440_nand_select_chip(void) +{ + int i; + struct s3c2440_nand * s3c2440nand = (struct s3c2440_nand *)0x4e000000; + s3c2440nand->nfcont &= ~(1<<1); + for(i=0; i<10; i++); +} + +/* 取消片選信號 */ +static void s3c2440_nand_deselect_chip(void) +{ + struct s3c2440_nand * s3c2440nand = (struct s3c2440_nand *)0x4e000000; + s3c2440nand->nfcont |= (1<<1); +} + +/* 發出命令 */ +static void s3c2440_write_cmd(int cmd) +{ + struct s3c2440_nand * s3c2440nand = (struct s3c2440_nand *)0x4e000000; + volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->nfcmd; + *p = cmd; +} + +/* 發出地址 */ +static void s3c2440_write_addr_lp(unsigned int addr) +{ + int i; + struct s3c2440_nand * s3c2440nand = (struct s3c2440_nand *)0x4e000000; + volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->nfaddr; + int col, page; + + col = addr & NAND_BLOCK_MASK_LP; + page = addr / NAND_SECTOR_SIZE_LP; + + *p = col & 0xff; /* Column Address A0~A7 */ + for(i=0; i<10; i++); + *p = (col >> 8) & 0x0f; /* Column Address A8~A11 */ + for(i=0; i<10; i++); + *p = page & 0xff; /* Row Address A12~A19 */ + for(i=0; i<10; i++); + *p = (page >> 8) & 0xff; /* Row Address A20~A27 */ + for(i=0; i<10; i++); + *p = (page >> 16) & 0x03; /* Row Address A28~A29 */ + for(i=0; i<10; i++); +} + +/* 讀取數據 */ +static unsigned char s3c2440_read_data(void) +{ + struct s3c2440_nand * s3c2440nand = (struct s3c2440_nand *)0x4e000000; + volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->nfdata; + return *p; +} + +/* 在第一次使用NAND Flash前，復位一下NAND Flash */ +static void nand_reset(void) +{ + s3c2440_nand_reset(); +} + +static void wait_idle(void) +{ + s3c2440_wait_idle(); +} + +static void nand_select_chip(void) +{ + int i; + s3c2440_nand_select_chip(); + for(i=0; i<10; i++); +} + +static void nand_deselect_chip(void) +{ + s3c2440_nand_deselect_chip(); +} + +static void write_cmd(int cmd) +{ + s3c2440_write_cmd(cmd); +} + +static void write_addr_lp(unsigned int addr) +{ + s3c2440_write_addr_lp(addr); +} + +static unsigned char read_data(void) +{ + return s3c2440_read_data(); +} + +/* 初始化NAND Flash */ +void nand_init_ll(void) +{ + struct s3c2440_nand * s3c2440nand = (struct s3c2440_nand *)0x4e000000; + + /* 設置時序 */ + s3c2440nand->nfconf = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4); + /* 使能NAND Flash控制器, 初始化ECC, 禁止片選 */ + s3c2440nand->nfcont = (1<<4)|(1<<1)|(1<<0); + + /* 復位NAND Flash */ + nand_reset(); +} + +/* 讀函數 + * Large Page + */ +extern void nand_read_ll_lp(unsigned char *buf, unsigned long start_addr, int size); +void nand_read_ll_lp(unsigned char *buf, unsigned long start_addr, int size) +{ + int i, j; + + if ((start_addr & NAND_BLOCK_MASK_LP) || (size & NAND_BLOCK_MASK_LP)) { + return ; /* 地址或長度不對齊 */ + } + + /* 選中芯片 */ + nand_select_chip(); + + for(i=start_addr; i < (start_addr + size);) { +#if 1 + if (((i / NAND_SECTOR_SIZE_LP) & NAND_PAGE_MASK_LP) == 0) { + if (nand_check_isbad(i) == -1) { + i += 0x20000; + size += 0x20000; + } + } +#endif + /* 發出READ0命令 */ + write_cmd(0); + + /* Write Address */ + write_addr_lp(i); + write_cmd(0x30); + wait_idle(); + + for(j=0; j < NAND_SECTOR_SIZE_LP; j++, i++) { + *buf = read_data(); + buf++; + } + } + + /* 取消片選信號 */ + nand_deselect_chip(); + + return ; +} + +int bBootFrmNORFlash(void) +{ + volatile unsigned int *pdw = (volatile unsigned int *)0; + unsigned int dwVal; + + /* + * 無論是從NOR Flash還是從NAND Flash啟動， + * 地址0處為指令"b Reset", 機器碼為0xEA00000B， + * 對于從NAND Flash啟動的情況，其開始4KB的代碼會復制到CPU內部4K內存中， + * 對于從NOR Flash啟動的情況，NOR Flash的開始地址即為0。 + * 對于NOR Flash，必須通過一定的命令序列才能寫數據， + * 所以可以根據這點差別來分辨是從NAND Flash還是NOR Flash啟動: + * 向地址0寫入一個數據，然后讀出來，如果沒有改變的話就是NOR Flash + */ + + dwVal = *pdw; + *pdw = 0x12345678; + if (*pdw != 0x12345678) + { + return 1; + } + else + { + *pdw = dwVal; + return 0; + } +} + +/* 檢查是否是壞塊 */ +int nand_check_isbad(unsigned int addr) +{ + int i; + struct s3c2440_nand * s3c2440nand = (struct s3c2440_nand *)0x4e000000; + volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->nfaddr; + int col, page; + unsigned char ret; + + if ((addr & NAND_BLOCK_MASK_LP)) + return -1; /* 地址或長度不對齊 */ + + /* 發出READ0命令 */ + write_cmd(0); + + /* Write Address */ + col = 2048; + page = (addr / NAND_SECTOR_SIZE_LP) & ~(NAND_PAGE_MASK_LP); + + *p = col & 0xff; /* Column Address A0~A7 */ + for(i=0; i<10; i++); + *p = (col >> 8) & 0x0f; /* Column Address A8~A11 */ + for(i=0; i<10; i++); + *p = page & 0xff; /* Row Address A12~A19 */ + for(i=0; i<10; i++); + *p = (page >> 8) & 0xff; /* Row Address A20~A27 */ + for(i=0; i<10; i++); + *p = (page >> 16) & 0x03; /* Row Address A28~A29 */ + for(i=0; i<10; i++); + write_cmd(0x30); + wait_idle(); + + ret = read_data(); + + if (ret == 0xff) + return 0; + else + return -1; +} + +int CopyCode2Ram(unsigned long start_addr, unsigned char *buf, int size) +{ + unsigned int *pdwDest; + unsigned int *pdwSrc; + int i; + + if (bBootFrmNORFlash()) + { + pdwDest = (unsigned int *)buf; + pdwSrc = (unsigned int *)start_addr; + /* 從 NOR Flash啟動 */ + for (i = 0; i < size / 4; i++) + { + pdwDest[i] = pdwSrc[i]; + } + return 0; + } + else + { + /* 初始化NAND Flash */ + nand_init_ll(); + /* 從 NAND Flash啟動 */ + nand_read_ll_lp(buf, start_addr, (size + NAND_BLOCK_MASK_LP)&~(NAND_BLOCK_MASK_LP)); + return 0; + } +} diff -uNr u-boot-2012.07/board/samsung/smdk2440/smdk2440.c u-boot-2012.07_fl2440/board/samsung/smdk2440/smdk2440.c --- u-boot-2012.07/board/samsung/smdk2440/smdk2440.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2012.07_fl2440/board/samsung/smdk2440/smdk2440.c 2012-10-19 17:04:02.000000000 +0800 @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002, 2010 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define FCLK_SPEED 2 + +#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ +#define M_MDIV 0xC3 +#define M_PDIV 0x4 +#define M_SDIV 0x1 +#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ +#define M_MDIV 0xA1 +#define M_PDIV 0x3 +#define M_SDIV 0x1 +#elif FCLK_SPEED==2 +#define M_MDIV 0x5C +#define M_PDIV 0x1 +#define M_SDIV 0x2 +#endif + +#define USB_CLOCK 2 +#if USB_CLOCK==0 +#define U_M_MDIV 0xA1 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x1 +#elif USB_CLOCK==1 +#define U_M_MDIV 0x48 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x2 +#elif USB_CLOCK==2 +#define U_M_MDIV 0x38 +#define U_M_PDIV 0x2 +#define U_M_SDIV 0x2 +#endif + +static inline void pll_delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_early_init_f(void) +{ + struct s3c24x0_clock_power * const clk_power = + s3c24x0_get_base_clock_power(); + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + writel(0xFFFFFF, &clk_power->locktime); + + /* configure MPLL */ + writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, + &clk_power->mpllcon); + + /* some delay between MPLL and UPLL */ + pll_delay(4000); + + /* configure UPLL */ + writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, + &clk_power->upllcon); + + /* some delay between MPLL and UPLL */ + pll_delay(8000); + + /* set up the I/O ports */ + writel(0x007FFFFF, &gpio->gpacon); + writel(0x00044555, &gpio->gpbcon); + writel(0x000007FF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x0000FFFF, &gpio->gpeup); + writel(0x000055AA, &gpio->gpfcon); + writel(0x000000FF, &gpio->gpfup); + writel(0xFF95FFBA, &gpio->gpgcon); + writel(0x0000FFFF, &gpio->gpgup); + writel(0x002AFAAA, &gpio->gphcon); + writel(0x000007FF, &gpio->gphup); + + return 0; +} + +int board_init(void) +{ + /* arch number of S3C2440-Board */ + gd->bd->bi_arch_number = MACH_TYPE_S3C2440; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + icache_enable(); + dcache_enable(); + + return 0; +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif +#ifdef CONFIG_DRIVER_DM9000 + rc = dm9000_initialize(bis); + if (eth_init(bis) < 0) { + eth_halt(); + printf("eth_init fail!\n"); + } +#endif + return rc; +} +#endif + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29LV800BB flash. + */ +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} + +/* lcdcon1 */ +#define CLKVAL(x) ((x)<<8) +#define PNRMODE(x) ((x)<<5) +#define BPPMODE(x) ((x)<<1) +/* lcdcon2 */ +#define VBPD(x) ((x)<<24) +#define LINEVAL(x) ((x)<<14) +#define VFPD(x) ((x)<<6) +#define VSPW(x) ((x)<<0) +/* lcdcon3 */ +#define HBPD(x) ((x)<<19) +#define HOZVAL(x) ((x)<<8) +#define HFPD(x) ((x)<<0) +/* lcdcon4 */ +#define HSPW(x) ((x)<<0) +/* lcdcon5 */ +#define FRM565(x) ((x)<<11) +#define PWREN(x) ((x)<<3) +#define HWSWP(x) ((x)<<0) + +#define TFT (3) +#define BPP16 (12) +#define TFT565 (1) + +void board_video_init(void) +{ + struct s3c24x0_lcd * const lcd = (struct s3c24x0_lcd *)0x4D000000; + + lcd->lcdcon1 = CLKVAL(7) | PNRMODE(TFT) | BPPMODE(BPP16); + lcd->lcdcon2 = VBPD(15) | LINEVAL(240-1) | VFPD(12) | VSPW(3); + lcd->lcdcon3 = HBPD(65) | HOZVAL(320-1) | HFPD(20); + lcd->lcdcon4 = HSPW(30); + lcd->lcdcon5 = FRM565(TFT565) | PWREN(1) | HWSWP(1); + +} \ No newline at end of file diff -uNr u-boot-2012.07/board/samsung/smdk2440/u-boot.lds u-boot-2012.07_fl2440/board/samsung/smdk2440/u-boot.lds --- u-boot-2012.07/board/samsung/smdk2440/u-boot.lds 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2012.07_fl2440/board/samsung/smdk2440/u-boot.lds 2012-10-01 20:50:13.000000000 +0800 @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __image_copy_start = .; + CPUDIR/start.o (.text) + board/samsung/smdk2440/libsmdk2440.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + _end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff -uNr u-boot-2012.07/boards.cfg u-boot-2012.07_fl2440/boards.cfg --- u-boot-2012.07/boards.cfg 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/boards.cfg 2012-10-01 10:55:46.000000000 +0800 @@ -63,6 +63,7 @@cm41xx arm arm920t - - ks8695VCMA9 arm arm920t vcma9 mpl s3c24x0smdk2410 arm arm920t - samsung s3c24x0 +smdk2440 arm arm920t - samsung s3c24x0omap1510inn arm arm925t - tiintegratorap_cm926ejs arm arm926ejs integrator armltd - integratorap:CM926EJ_Sintegratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp:CM924EJ_S diff -uNr u-boot-2012.07/common/cmd_menu.c u-boot-2012.07_fl2440/common/cmd_menu.c --- u-boot-2012.07/common/cmd_menu.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2012.07_fl2440/common/cmd_menu.c 2012-10-08 22:39:36.000000000 +0800 @@ -0,0 +1,124 @@ +#include <common.h> +#include <command.h> + +extern char console_buffer[]; +static char awaitkey(unsigned long delay, int* error_p) +{ + int i; + + if (delay == -1) { + while (1) { + if (tstc()) /* we got a key press */ + return getc(); + } + } + else { + for (i = 0; i < delay; i++) { + if (tstc()) /* we got a key press */ + return getc(); + udelay (10*1000); + } + } + if (error_p) + *error_p = -1; + return 0; +} + +void main_menu_usage(void) +{ + printf("\r\n##### tftp menu for SMDK2440 #####\r\n"); + + printf("[1] Download u-boot.bin to Nand Flash\r\n"); + printf("[2] Download uImage to Nand Flash\r\n"); + printf("[3] Download root_yaffs2to Nand Flash\r\n"); + printf("[4] Download u-boot.bin to SDRAM &Run\r\n"); + printf("[5] Download uImage to SDRAM &Run\r\n"); + printf("[b] Boot the system\r\n"); + printf("[r] Reboot u-boot\r\n"); + printf("[q] Quit from menu\r\n"); + printf("Enter your selection: "); +} + +void menu_shell(void) +{ + char c; + char cmd_buf[200]; + + while (1) + { + main_menu_usage(); + c = awaitkey(-1, NULL); + printf("%c\n", c); + switch (c) + { + case '1': + { + strcpy(cmd_buf, "tftp 0x31000000 u-boot.bin; nand erase.part bootloader; nand write.jffs2 0x31000000 bootloader"); + run_command(cmd_buf, 0); + break; + } + case '2': + { + strcpy(cmd_buf, "tftp 0x31000000 uImage; nand erase.part kernel; nand write.jffs2 0x31000000 kernel"); + run_command(cmd_buf, 0); + break; + } + + case '3': + { + strcpy(cmd_buf, "tftp 0x31000000 root_yaffs2; nand erase.part root; nand write.yaffs 0x31000000 0x460000 0x528000"); + run_command(cmd_buf, 0); + break; + } + + case '4': + { + strcpy(cmd_buf, "tftp 0x31000000 u-boot.bin; go 0x31000000"); + run_command(cmd_buf, 0); + break; + } + case '5': + { + strcpy(cmd_buf, "tftp 0x30007FC0 uImage; bootm 0x30007FC0"); + run_command(cmd_buf, 0); + break; + } + + case 'b': + { + printf("Booting Linux ...\n"); + strcpy(cmd_buf, "nand read.jffs2 0x30007FC0 kernel; bootm 0x30007FC0"); + run_command(cmd_buf, 0); + break; + } + + case 'r': + { + strcpy(cmd_buf, "reset"); + run_command(cmd_buf, 0); + break; + } + + case 'q': + { + return; + break; + } + + } + + } +} + +int do_menu (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + menu_shell(); + return 0; +} + +U_BOOT_CMD( + menu, 3, 0, do_menu, + "menu - display a menu, to select the items to do something\n", + " - display a menu, to select the items to do something" +); + diff -uNr u-boot-2012.07/common/cmd_nand.c u-boot-2012.07_fl2440/common/cmd_nand.c --- u-boot-2012.07/common/cmd_nand.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/common/cmd_nand.c 2012-10-10 22:26:01.000000000 +0800 @@ -668,7 +668,7 @@}ret = nand_write_skip_bad(nand, off, &rwsize,(u_char *)addr, - WITH_INLINE_OOB); + WITH_YAFFS_OOB);#endif} else if (!strcmp(s, ".oob")) {/* out-of-band data */ diff -uNr u-boot-2012.07/common/main.c u-boot-2012.07_fl2440/common/main.c --- u-boot-2012.07/common/main.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/common/main.c 2012-10-06 10:07:00.000000000 +0800 @@ -397,6 +397,10 @@#endif /* CONFIG_MENUKEY */#endif /* CONFIG_BOOTDELAY */+#ifdef CONFIG_SMDK2440 + run_command("menu", 0); /* tftp menu */ + nand_read_ll_lp(0x32000000, 0, 0x100000); +#endif/** Main Loop for Monitor Command Processing*/ diff -uNr u-boot-2012.07/common/Makefile u-boot-2012.07_fl2440/common/Makefile --- u-boot-2012.07/common/Makefile 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/common/Makefile 2012-10-03 20:02:52.000000000 +0800 @@ -193,7 +193,7 @@COBJS-y += image.oCOBJS-y += memsize.oCOBJS-y += stdio.o - +COBJS-y += cmd_menu.oCOBJS := $(sort $(COBJS-y))XCOBJS := $(sort $(XCOBJS-y)) diff -uNr u-boot-2012.07/common/serial.c u-boot-2012.07_fl2440/common/serial.c --- u-boot-2012.07/common/serial.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/common/serial.c 2012-10-01 15:48:50.000000000 +0800 @@ -80,7 +80,7 @@#if defined(CONFIG_STUART)serial_register(&serial_stuart_device);#endif -#if defined(CONFIG_S3C2410) +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)serial_register(&s3c24xx_serial0_device);serial_register(&s3c24xx_serial1_device);serial_register(&s3c24xx_serial2_device); diff -uNr u-boot-2012.07/drivers/i2c/s3c24x0_i2c.c u-boot-2012.07_fl2440/drivers/i2c/s3c24x0_i2c.c --- u-boot-2012.07/drivers/i2c/s3c24x0_i2c.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/drivers/i2c/s3c24x0_i2c.c 2012-10-01 15:50:46.000000000 +0800 @@ -57,7 +57,7 @@{struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();-#ifdef CONFIG_S3C2410 +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)return (readl(&gpio->gpedat) & 0x8000) >> 15;#endif#ifdef CONFIG_S3C2400 @@ -76,7 +76,7 @@{struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();-#ifdef CONFIG_S3C2410 +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat);#endif#ifdef CONFIG_S3C2400 @@ -128,7 +128,7 @@}if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) { -#ifdef CONFIG_S3C2410 +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)ulong old_gpecon = readl(&gpio->gpecon);#endif#ifdef CONFIG_S3C2400 @@ -137,7 +137,7 @@/* bus still busy probably by (most) previously interruptedtransfer */-#ifdef CONFIG_S3C2410 +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,&gpio->gpecon); @@ -163,7 +163,7 @@udelay(1000);/* restore pin functions */ -#ifdef CONFIG_S3C2410 +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)writel(old_gpecon, &gpio->gpecon);#endif#ifdef CONFIG_S3C2400 diff -uNr u-boot-2012.07/drivers/mtd/nand/Makefile u-boot-2012.07_fl2440/drivers/mtd/nand/Makefile --- u-boot-2012.07/drivers/mtd/nand/Makefile 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/drivers/mtd/nand/Makefile 2012-10-01 16:36:59.000000000 +0800 @@ -60,6 +60,7 @@COBJS-$(CONFIG_NAND_NDFC) += ndfc.oCOBJS-$(CONFIG_NAND_NOMADIK) += nomadik.oCOBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o +COBJS-$(CONFIG_NAND_S3C2440) += s3c2440_nand.oCOBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.oCOBJS-$(CONFIG_NAND_SPEAR) += spr_nand.oCOBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o diff -uNr u-boot-2012.07/drivers/mtd/nand/nand_base.c u-boot-2012.07_fl2440/drivers/mtd/nand/nand_base.c --- u-boot-2012.07/drivers/mtd/nand/nand_base.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/drivers/mtd/nand/nand_base.c 2012-10-10 22:20:35.000000000 +0800 @@ -1986,7 +1986,6 @@oob = nand_fill_oob(chip, oob, len, ops);oobwritelen -= len;} -ret = chip->write_page(mtd, chip, wbuf, page, cached,(ops->mode == MTD_OOB_RAW));if (ret) @@ -2030,7 +2029,7 @@{struct nand_chip *chip = mtd->priv;int ret; - + /* Do not allow writes past end of device */if ((to + len) > mtd->size)return -EINVAL; @@ -2145,7 +2144,6 @@int ret = -ENOTSUPP;ops->retlen = 0; -/* Do not allow writes past end of device */if (ops->datbuf && (to + ops->len) > mtd->size) {MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " @@ -2166,9 +2164,13 @@}if (!ops->datbuf) + {ret = nand_do_write_oob(mtd, to, ops); + }else + {ret = nand_do_write_ops(mtd, to, ops); + }out:nand_release_device(mtd); diff -uNr u-boot-2012.07/drivers/mtd/nand/nand_util.c u-boot-2012.07_fl2440/drivers/mtd/nand/nand_util.c --- u-boot-2012.07/drivers/mtd/nand/nand_util.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/drivers/mtd/nand/nand_util.c 2012-10-19 17:03:37.000000000 +0800 @@ -507,7 +507,7 @@*length = 0;return -EINVAL;} - +#if 0need_skip = check_skip_len(nand, offset, *length);if (need_skip < 0) {printf ("Attempt to write outside the flash area\n"); @@ -519,13 +519,12 @@rval = nand_write (nand, offset, length, buffer);if (rval == 0)return 0; -*length = 0;printf ("NAND write to offset %llx failed %d\n",offset, rval);return rval;} - +#endifwhile (left_to_write > 0) {size_t block_offset = offset & (nand->erasesize - 1);size_t write_size, truncated_write_size; @@ -553,7 +552,7 @@ops.len = pagesize;ops.ooblen = nand->oobsize; - ops.mode = MTD_OOB_AUTO; + ops.mode = MTD_OOB_RAW;ops.ooboffs = 0;pages = write_size / pagesize_oob; @@ -565,7 +564,9 @@rval = nand->write_oob(nand, offset, &ops);if (rval != 0) + {break; + }offset += pagesize;p_buffer += pagesize_oob; diff -uNr u-boot-2012.07/drivers/mtd/nand/s3c2440_nand.c u-boot-2012.07_fl2440/drivers/mtd/nand/s3c2440_nand.c --- u-boot-2012.07/drivers/mtd/nand/s3c2440_nand.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2012.07_fl2440/drivers/mtd/nand/s3c2440_nand.c 2012-10-02 20:24:36.000000000 +0800 @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2006 OpenMoko, Inc. + * Author: Harald Welte <laforge@openmoko.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <nand.h> +#include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> + + +#define S3C2440_NFCONF_TACLS(x) ((x)<<12) +#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) +#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) +#define S3C2440_NFCONF_2048BYTE (1<<2) +#define S3C2440_NFCONF_4STEP (1<<1) + +#define S3C2440_NFCONT_INITECC (1<<4) +#define S3C2440_NFCONT_nFCE (1<<1) +#define S3C2440_NFCONT_EN (1<<0) + +#define S3C2440_ADDR_NALE 0x08 +#define S3C2440_ADDR_NCLE 0x0C + +#ifdef CONFIG_NAND_SPL + +/* in the early stage of NAND flash booting, printf() is not available */ +#define printf(fmt, args...) + +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i = 0; i < len; i++) + buf[i] = readb(this->IO_ADDR_R); +} +#endif + +static void s3c2440_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *chip = mtd->priv; + struct s3c2440_nand *nand = s3c2440_get_base_nand(); + + debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong)nand; + + if (!(ctrl & NAND_CLE)) /* not command */ + IO_ADDR_W |= S3C2440_ADDR_NCLE; + if (!(ctrl & NAND_ALE)) /* not address */ + IO_ADDR_W |= S3C2440_ADDR_NALE; + + if(cmd ==NAND_CMD_NONE) + IO_ADDR_W = &nand->nfdata; + + chip->IO_ADDR_W = (void *)IO_ADDR_W; + + if (ctrl & NAND_NCE) + writel(readl(&nand->nfcont) & ~S3C2440_NFCONT_nFCE, + &nand->nfcont); + else + writel(readl(&nand->nfcont) | S3C2440_NFCONT_nFCE, + &nand->nfcont); + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, chip->IO_ADDR_W); +} + +static int s3c2440_dev_ready(struct mtd_info *mtd) +{ + struct s3c2440_nand *nand = s3c2440_get_base_nand(); + debug("dev_ready\n"); + return readl(&nand->nfstat) & 0x01; +} + +#ifdef CONFIG_S3C2440_NAND_HWECC +void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{ + struct s3c2440_nand *nand = s3c2440_get_base_nand(); + debug("s3c2440_nand_enable_hwecc(%p, %d)\n", mtd, mode); + writel(readl(&nand->nfcont) | S3C2440_NFCONT_INITECC, &nand->nfcont); +} + +static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) +{ + struct s3c2440_nand *nand = s3c2440_get_base_nand(); + ecc_code[0] = readb(&nand->nfeccd); + ecc_code[1] = readb(&nand->nfeccd + 1); + ecc_code[2] = readb(&nand->nfeccd + 2); + ecc_code[3] = readb(&nand->nfeccd + 3); + debug("s3c2440_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", + mtd , ecc_code[0], ecc_code[1], ecc_code[2], ecc_code[4]); + + return 0; +} + +static int s3c2440_nand_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + if (read_ecc[0] == calc_ecc[0] && + read_ecc[1] == calc_ecc[1] && + read_ecc[2] == calc_ecc[2] && + read_ecc[3] == calc_ecc[3]) + return 0; + + printf("s3c2440_nand_correct_data: not implemented\n"); + return -1; +} +#endif + +int board_nand_init(struct nand_chip *nand) +{ + u_int32_t cfg; + u_int8_t tacls, twrph0, twrph1; + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + struct s3c2440_nand *nand_reg = s3c2440_get_base_nand(); + + debug("board_nand_init()\n"); + + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); + + /* initialize hardware */ +#if defined(CONFIG_S3C2440_CUSTOM_NAND_TIMING) + tacls = CONFIG_S3C2440_TACLS; + twrph0 = CONFIG_S3C2440_TWRPH0; + twrph1 = CONFIG_S3C2440_TWRPH1; +#else + tacls = 4; + twrph0 = 8; + twrph1 = 8; +#endif + + cfg |= S3C2440_NFCONF_TACLS(tacls); + cfg |= S3C2440_NFCONF_TWRPH0(twrph0); + cfg |= S3C2440_NFCONF_TWRPH1(twrph1); + writel(cfg, &nand_reg->nfconf); + + cfg = S3C2440_NFCONT_INITECC; + cfg |= S3C2440_NFCONT_nFCE; + cfg |= S3C2440_NFCONT_EN; + writel(cfg, &nand_reg->nfcont); + + /* initialize nand_chip data structure */ + nand->IO_ADDR_R = (void *)&nand_reg->nfdata; + nand->IO_ADDR_W = (void *)&nand_reg->nfdata; + + nand->select_chip = NULL; + + /* read_buf and write_buf are default */ + /* read_byte and write_byte are default */ +#ifdef CONFIG_NAND_SPL + nand->read_buf = nand_read_buf; +#endif + + /* hwcontrol always must be implemented */ + nand->cmd_ctrl = s3c2440_hwcontrol; + + nand->dev_ready = s3c2440_dev_ready; + +#ifdef CONFIG_S3C2440_NAND_HWECC + nand->ecc.hwctl = s3c2440_nand_enable_hwecc; + nand->ecc.calculate = s3c2440_nand_calculate_ecc; + nand->ecc.correct = s3c2440_nand_correct_data; + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; +#else + nand->ecc.mode = NAND_ECC_SOFT; +#endif + +#ifdef CONFIG_S3C2440_NAND_BBT + nand->options = NAND_USE_FLASH_BBT; +#else + nand->options = 0; +#endif + + debug("end of nand_init\n"); + + return 0; +} diff -uNr u-boot-2012.07/drivers/net/dm9000x.c u-boot-2012.07_fl2440/drivers/net/dm9000x.c --- u-boot-2012.07/drivers/net/dm9000x.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/drivers/net/dm9000x.c 2012-10-03 17:44:48.000000000 +0800 @@ -240,11 +240,11 @@id_val |= DM9000_ior(DM9000_PIDL) << 16;id_val |= DM9000_ior(DM9000_PIDH) << 24;if (id_val == DM9000_ID) { - printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE, + debug("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,id_val);return 0;} else { - printf("dm9000 not found at 0x%08x id: 0x%08x\n", + debug("dm9000 not found at 0x%08x id: 0x%08x\n",CONFIG_DM9000_BASE, id_val);return -1;} @@ -306,26 +306,26 @@switch (io_mode) {case 0x0: /* 16-bit mode */ - printf("DM9000: running in 16 bit mode\n"); + debug("DM9000: running in 16 bit mode\n");db->outblk = dm9000_outblk_16bit;db->inblk = dm9000_inblk_16bit;db->rx_status = dm9000_rx_status_16bit;break;case 0x01: /* 32-bit mode */ - printf("DM9000: running in 32 bit mode\n"); + debug("DM9000: running in 32 bit mode\n");db->outblk = dm9000_outblk_32bit;db->inblk = dm9000_inblk_32bit;db->rx_status = dm9000_rx_status_32bit;break;case 0x02: /* 8 bit mode */ - printf("DM9000: running in 8 bit mode\n"); + debug("DM9000: running in 8 bit mode\n");db->outblk = dm9000_outblk_8bit;db->inblk = dm9000_inblk_8bit;db->rx_status = dm9000_rx_status_8bit;break;default:/* Assume 8 bit mode, will probably not work anyway */ - printf("DM9000: Undefined IO-mode:0x%x\n", io_mode); + debug("DM9000: Undefined IO-mode:0x%x\n", io_mode);db->outblk = dm9000_outblk_8bit;db->inblk = dm9000_inblk_8bit;db->rx_status = dm9000_rx_status_8bit; @@ -349,7 +349,7 @@/* Clear interrupt status */DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);- printf("MAC: %pM\n", dev->enetaddr); + debug("MAC: %pM\n", dev->enetaddr);/* fill device MAC address registers */for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) @@ -367,7 +367,8 @@DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);/* Enable TX/RX interrupt mask */DM9000_iow(DM9000_IMR, IMR_PAR); - + +#if 0i = 0;while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */udelay(1000); @@ -377,28 +378,28 @@return 0;}} - +#endif/* see what we've got */lnk = dm9000_phy_read(17) >> 12; - printf("operating at "); + debug("operating at ");switch (lnk) {case 1: - printf("10M half duplex "); + debug("10M half duplex ");break;case 2: - printf("10M full duplex "); + debug("10M full duplex ");break;case 4: - printf("100M half duplex "); + debug("100M half duplex ");break;case 8: - printf("100M full duplex "); + debug("100M full duplex ");break;default: - printf("unknown: %d ", lnk); + debug("unknown: %d ", lnk);break;} - printf("mode\n"); + debug("mode\n");return 0;}@@ -449,6 +450,7 @@*/static void dm9000_halt(struct eth_device *netdev){ +#if 0DM9000_DBG("%s\n", __func__);/* RESET devie */ @@ -456,6 +458,7 @@DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */ +#endif}/* @@ -595,7 +598,7 @@/* Fill the phyxcer register into REG_0C */DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ - udelay(100); /* Wait read complete */ + udelay(1000); /* Wait read complete */DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);diff -uNr u-boot-2012.07/drivers/video/cfb_console.c u-boot-2012.07_fl2440/drivers/video/cfb_console.c --- u-boot-2012.07/drivers/video/cfb_console.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/drivers/video/cfb_console.c 2012-10-05 20:03:21.000000000 +0800 @@ -297,8 +297,8 @@#define VIDEO_LOGO_LUT_OFFSET LINUX_LOGO_LUT_OFFSET#define VIDEO_LOGO_COLORS LINUX_LOGO_COLORS#endif /* CONFIG_VIDEO_BMP_LOGO */ -#define VIDEO_INFO_X (VIDEO_LOGO_WIDTH) -#define VIDEO_INFO_Y (VIDEO_FONT_HEIGHT/2) +#define VIDEO_INFO_X (0) +#define VIDEO_INFO_Y (VIDEO_LOGO_HEIGHT)#else /* CONFIG_VIDEO_LOGO */#define VIDEO_LOGO_WIDTH 0#define VIDEO_LOGO_HEIGHT 0 @@ -501,7 +501,6 @@for (rows = VIDEO_FONT_HEIGHT, dest = dest0;rows--; dest += VIDEO_LINE_LEN) {u8 bits = *cdat++; -((u32 *) dest)[0] =SHORTSWAP32((video_font_draw_table16[bits >> 6] & eorx) ^ @@ -598,11 +597,18 @@}}+#ifdef CONFIG_VIDEO_SMDK2440 +extern void video_drawstring(int xx, int yy, unsigned char *s); +void video_drawstring(int xx, int yy, unsigned char *s) +{ + video_drawchars(xx, yy, s, strlen((char *) s)); +} +#elsestatic inline void video_drawstring(int xx, int yy, unsigned char *s){video_drawchars(xx, yy, s, strlen((char *) s));} - +#endifstatic void video_putchar(int xx, int yy, unsigned char c){video_drawchars(xx, yy + video_logo_height, &c, 1); @@ -1628,7 +1634,7 @@#endif /* CONFIG_SPLASH_SCREEN */logo_plot(video_fb_address, VIDEO_COLS, 0, 0); - +#ifdef CONFIG_CONSOLE_EXTRA_INFOsprintf(info, " %s", version_string);space = (VIDEO_LINE_LEN / 2 - VIDEO_INFO_X) / VIDEO_FONT_WIDTH; @@ -1643,8 +1649,6 @@y_off = 1;} elsevideo_drawstring(VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *) info); - -#ifdef CONFIG_CONSOLE_EXTRA_INFO{int i, n =((video_logo_height - @@ -1799,6 +1803,10 @@debug("Video: Drawing the logo ...\n");video_console_address = video_logo();#else +#ifdef CONFIG_VIDEO_SMDK2440 + /* draw logo */ + draw_logo(pGD); +#endifvideo_console_address = video_fb_address;#endifdiff -uNr u-boot-2012.07/drivers/video/Makefile u-boot-2012.07_fl2440/drivers/video/Makefile --- u-boot-2012.07/drivers/video/Makefile 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/drivers/video/Makefile 2012-10-04 11:28:27.000000000 +0800 @@ -48,6 +48,7 @@COBJS-$(CONFIG_VIDEO_SM501) += sm501.oCOBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.oCOBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o +COBJS-$(CONFIG_VIDEO_SMDK2440) += smdk2440_fb.o videomodes.oCOBJS := $(sort $(COBJS-y))SRCS := $(COBJS:.o=.c) diff -uNr u-boot-2012.07/drivers/video/smdk2440_fb.c u-boot-2012.07_fl2440/drivers/video/smdk2440_fb.c --- u-boot-2012.07/drivers/video/smdk2440_fb.c 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2012.07_fl2440/drivers/video/smdk2440_fb.c 2012-10-05 20:12:24.000000000 +0800 @@ -0,0 +1,141 @@ +#include <common.h> +#include <malloc.h> +#include <video_fb.h> +#include <video_font.h> +#include "videomodes.h" +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h> + +extern void board_video_init(void); +extern void draw_logo(GraphicDevice *pGD); +GraphicDevice smi; + +void draw_logo(GraphicDevice *pGD) +{ + int i, j; + int col, row; + char *motd = "uboot-for-smdk2440"; + for (i = 0; i < 240; i++) { + for (j = 0; j < 320; j++) { + *((volatile unsigned char *)pGD->frameAdrs + i*320*2 + j*2 + 0) = 0x00; + *((volatile unsigned char *)pGD->frameAdrs + i*320*2 + j*2 + 1) = 0x00; + } + } + /* 20col 15row */ + row = 8 * VIDEO_FONT_HEIGHT; + col = 12 * VIDEO_FONT_WIDTH; + video_drawstring(col, row, (uchar *) motd); +} +/******************************************************************************* + * + * Init video chip with common Linux graphic modes (lilo) + */ +void *video_hw_init (void) +{ + struct s3c24x0_lcd * const lcd = (struct s3c24x0_lcd *)0x4D000000; + GraphicDevice *pGD = (GraphicDevice *)&smi; + int videomode; + unsigned long t1, hsynch, vsynch; + char *penv; + int tmp, i, bits_per_pixel; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; + //unsigned char videoout; + + /* Search for video chip */ + printf("Video: "); + + tmp = 0; + videomode = 0x300; /* 320*240 */ + + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } + else + tmp = 1; + + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); + i = 0; + } + res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; + bits_per_pixel = vesa_modes[i].bits_per_pixel; + } + else { + res_mode = (struct ctfb_res_modes *) &var_mode; + bits_per_pixel = video_get_params (res_mode, penv); + } + + /* calculate hsynch and vsynch freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsynch = 1000000000L / t1; + t1 *= (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsynch = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bits_per_pixel, (hsynch / 1000), + (vsynch / 1000)); + + printf ("%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->plnSizeX = res_mode->xres; + pGD->plnSizeY = res_mode->yres; + + + switch (bits_per_pixel) { + case 8: + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + break; + case 15: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_15BIT_555RGB; + break; + case 16: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_16BIT_565RGB; + break; + case 24: + pGD->gdfBytesPP = 3; + pGD->gdfIndex = GDF_24BIT_888RGB; + break; + } + + /* warning: uboot malloc size is CONFIG_SYS_MALLOC_LEN */ + pGD->memSize = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP; + pGD->frameAdrs = (unsigned long)malloc(pGD->memSize); + + board_video_init(); + + lcd->lcdsaddr1 = pGD->frameAdrs >> 1; + lcd->lcdsaddr2 = (lcd->lcdsaddr1&0x1fffff) + (pGD->winSizeX+0) * pGD->winSizeY; + lcd->lcdsaddr3 = (pGD->winSizeX & 0x7ff); + + /* Clear video memory */ + memset((void *)pGD->frameAdrs, 0, pGD->memSize); + + /* Enable Display */ + lcd->lcdcon1 |= 0x01; /* ENVID = 1 */ + + return ((void*)&smi); + } \ No newline at end of file diff -uNr u-boot-2012.07/drivers/video/videomodes.c u-boot-2012.07_fl2440/drivers/video/videomodes.c --- u-boot-2012.07/drivers/video/videomodes.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/drivers/video/videomodes.c 2012-10-04 14:06:51.000000000 +0800 @@ -79,6 +79,7 @@#include "videomodes.h"const struct ctfb_vesa_modes vesa_modes[VESA_MODES_COUNT] = { + {0x300, RES_MODE_320x240, 16},{0x301, RES_MODE_640x480, 8},{0x310, RES_MODE_640x480, 15},{0x311, RES_MODE_640x480, 16}, @@ -107,6 +108,7 @@{960, 720, 13100, 160, 40, 32, 8, 80, 4, 0, FB_VMODE_NONINTERLACED},{1152, 864, 12004, 200, 64, 32, 16, 80, 4, 0, FB_VMODE_NONINTERLACED},{1280, 1024, 9090, 200, 48, 26, 1, 184, 3, 0, FB_VMODE_NONINTERLACED}, + {320, 240, 160000, 65, 20, 15, 12, 30, 3, 0, FB_VMODE_NONINTERLACED}, };/************************************************************************ diff -uNr u-boot-2012.07/drivers/video/videomodes.h u-boot-2012.07_fl2440/drivers/video/videomodes.h --- u-boot-2012.07/drivers/video/videomodes.h 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/drivers/video/videomodes.h 2012-10-04 09:38:29.000000000 +0800 @@ -78,9 +78,10 @@#define RES_MODE_960_720 3#define RES_MODE_1152x864 4#define RES_MODE_1280x1024 5 -#define RES_MODES_COUNT 6 +#define RES_MODE_320x240 6 +#define RES_MODES_COUNT 7-#define VESA_MODES_COUNT 19 +#define VESA_MODES_COUNT 20extern const struct ctfb_vesa_modes vesa_modes[];extern const struct ctfb_res_modes res_mode_init[]; diff -uNr u-boot-2012.07/include/configs/smdk2440.h u-boot-2012.07_fl2440/include/configs/smdk2440.h --- u-boot-2012.07/include/configs/smdk2440.h 1970-01-01 08:00:00.000000000 +0800 +++ u-boot-2012.07_fl2440/include/configs/smdk2440.h 2012-10-07 21:40:55.000000000 +0800 @@ -0,0 +1,266 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * Gary Jennejohn <garyj@denx.de> + * David Mueller <d.mueller@elsoft.ch> + * + * Configuation settings for the SAMSUNG SMDK2440 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARM920T /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2440 /* specifically a SAMSUNG S3C2440 SoC */ +#define CONFIG_SMDK2440 /* on a SAMSUNG SMDK2440 Board */ + +#define CONFIG_SYS_CLK_FREQ 12000000 +#define CONFIG_SYS_TEXT_BASE 0x31000000 +#define CONFIG_SYS_LDSCRIPT "board/samsung/smdk2440/u-boot.lds" +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * bootm support + */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * NET support + */ +#define CONFIG_DRIVER_DM9000 +#define CONFIG_DM9000_NO_SROM +#define CONFIG_DM9000_BASE 0x20000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+4) + +/* + * LCD support + */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SMDK2440 +#if 0 +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#define CONFIG_CFB_CONSOLE +#define VIDEO_KBD_INIT_FCT 0 +#define VIDEO_FB_16BPP_WORD_SWAP +#define VIDEO_TSTC_FCT serial_tstc +#define VIDEO_GETC_FCT serial_getc +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#if 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "" +#endif +/* + * serial support + */ +#define CONFIG_S3C24X0_SERIAL +#define CONFIG_SERIAL1 /* we use SERIAL 1 on SMDK2440 */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_BAUDRATE 115200 + + +/* + * USB support (currently only works with D-cache off) + */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_KEYBOARD +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION + +/* + * RTC + */ +#define CONFIG_RTC_S3C24X0 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#if 1 +#define CONFIG_CMD_BSP +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_USB +#endif +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING + + +/* + * environment organization. + */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_SIZE 0x40000 +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTARGS "noinitrd root=/dev/mtdblock3 init=/linuxrc console=ttySAC0 rootfstype=yaffs2" +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.7.17 +#define CONFIG_SERVERIP 192.168.7.11 +#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x30007FC0 kernel; bootm 0x30007FC0" + +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "SMDK2440# " +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1+PHYS_SDRAM_1_SIZE /* 64 MB in DRAM */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_HZ 1000 + +/* support additional compression methods */ +#define CONFIG_BZIP2 +#define CONFIG_LZO +#define CONFIG_LZMA + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #6 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x08000000 /* Flash Bank #1 */ + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +/* + * FLASH + */ +#define CONFIG_INTEL_JS28F320 +/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 32 + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +/* + * Size of malloc() pool + * BZIP2 / LZO / LZMA need a lot of RAM + */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_S3C2440 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x4E000000 + +#define CONFIG_S3C2440_CUSTOM_NAND_TIMING +#define CONFIG_S3C2440_TACLS 0 +#define CONFIG_S3C2440_TWRPH0 3 +#define CONFIG_S3C2440_TWRPH1 0 + +#if 0 +#define CONFIG_S3C2440_NAND_HWECC +#define CONFIG_SYS_NAND_ECCSIZE 2048 +#define CONFIG_SYS_NAND_ECCBYTES 4 +#endif +#endif + +/* + * File system + */ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_NAND_YAFFS +#define CONFIG_YAFFS2 +#define CONFIG_RBTREE + +#define MTDIDS_DEFAULT "nand0=nandflash0" +#define MTDPARTS_DEFAULT "mtdparts=nandflash0:1m@0(bootloader)," \ + "256k(params)," \ + "3m(kernel)," \ + "-(root)" + +#endif /* __CONFIG_H */ diff -uNr u-boot-2012.07/include/serial.h u-boot-2012.07_fl2440/include/serial.h --- u-boot-2012.07/include/serial.h 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/include/serial.h 2012-10-01 15:54:10.000000000 +0800 @@ -57,7 +57,7 @@extern struct serial_device uartlite_serial3_device;#endif-#if defined(CONFIG_S3C2410) +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)extern struct serial_device s3c24xx_serial0_device;extern struct serial_device s3c24xx_serial1_device;extern struct serial_device s3c24xx_serial2_device; diff -uNr u-boot-2012.07/lib/display_options.c u-boot-2012.07_fl2440/lib/display_options.c --- u-boot-2012.07/lib/display_options.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/lib/display_options.c 2012-10-03 20:35:12.000000000 +0800 @@ -76,7 +76,7 @@}}- printf ("%lu", n); + printf ("%3lu", n);if (m) {printf (".%ld", m);} diff -uNr u-boot-2012.07/net/net.c u-boot-2012.07_fl2440/net/net.c --- u-boot-2012.07/net/net.c 2012-07-31 02:24:37.000000000 +0800 +++ u-boot-2012.07_fl2440/net/net.c 2012-10-03 17:43:02.000000000 +0800 @@ -317,11 +317,12 @@net_init();eth_halt();eth_set_current(); +#if 0if (eth_init(bd) < 0) {eth_halt();return -1;} - +#endifrestart:net_set_state(NETLOOP_CONTINUE);

轉載于:https://www.cnblogs.com/ziqiuqiandao/archive/2012/10/22/2734602.html

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