本文發(fā)布于www.hackster.io，由東京理工大學(xué)的計(jì)算機(jī)學(xué)院開發(fā)，專用于教學(xué)與加速用(蘇老師也一直認(rèn)為這是RISC-V當(dāng)前的主要方向)。

目前市場上開源的RISC-V內(nèi)核已經(jīng)很多，但很少有公開的RISC-V計(jì)算系統(tǒng)是非常輕型且能跑Linux系統(tǒng)的。

這一款RISC-V內(nèi)核就可以運(yùn)行在FPGA上，用Verilog編寫的，需要很少硬件的資源就能跑起來，所以可以運(yùn)行在一個(gè)低成本的FPGA上。

來看一下詳細(xì)的技術(shù)介紹：

占用很少的FPGA資源

The resulting design, dubbed RVSoC, implements the 32-bit RV32IMAC instruction set architecture and offers a 12-stage pipeline with a memory management unit (MMU) - not strictly required for booting Linux, given the kernel's support for manual memory mapping in the event of no hardware MMU being available, but definitely a nice-to-have for all but the most basic of possible uses. Despite this, the design comes in at a mere 5,000 lines of Verilog HDL.

"We are planning to release the RTL code of the designed RVSoC as an open and royalty free RTL design," the team pledges. "Because RVSoC is a computer system that supports Linux and uses a small amount of hardware resources, it can be applied to various purposes. A feature of RISC-V is that it has a room for the extended instructions by computer system developers. The ability of extension can be the basic requirement for application-specific accelerators and it enables to implement more specialised instruction sets.

性能相當(dāng)于i386和i486之間的處理器

"The resource-saving of RVSoC can be suitable for the implementation of various accelerators and special processor cores by adding unique instructions, and the development of related software.The number of lines in Verilog HDL code of RVSoC is about 5,000, and it is relatively easy to understand the entire implementation of the Linux capable computer system. Therefore, it is suitable to be used as a sample computer system of the education on computer science."

關(guān)于該處理器的詳細(xì)技術(shù)文章介紹，點(diǎn)擊左下角的“閱讀原文”。

要了解更多的關(guān)于RISC V在FPGA上的移植和嵌入式應(yīng)用，可以參考硬禾學(xué)堂聯(lián)合清華大學(xué)出版社推出的“基于FPGA與RISC-V的嵌入式系統(tǒng)設(shè)計(jì)”教程，本書作者為RISCV基金會(huì)發(fā)起的Soft CPU 2019年度的冠軍。

與50位技術(shù)專家面對(duì)面20年技術(shù)見證，附贈(zèng)技術(shù)全景圖

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