本文發布于www.hackster.io，由東京理工大學的計算機學院開發，專用于教學與加速用(蘇老師也一直認為這是RISC-V當前的主要方向)。

目前市場上開源的RISC-V內核已經很多，但很少有公開的RISC-V計算系統是非常輕型且能跑Linux系統的。

這一款RISC-V內核就可以運行在FPGA上，用Verilog編寫的，需要很少硬件的資源就能跑起來，所以可以運行在一個低成本的FPGA上。

來看一下詳細的技術介紹：

占用很少的FPGA資源

The resulting design, dubbed RVSoC, implements the 32-bit RV32IMAC instruction set architecture and offers a 12-stage pipeline with a memory management unit (MMU) - not strictly required for booting Linux, given the kernel's support for manual memory mapping in the event of no hardware MMU being available, but definitely a nice-to-have for all but the most basic of possible uses. Despite this, the design comes in at a mere 5,000 lines of Verilog HDL.

"We are planning to release the RTL code of the designed RVSoC as an open and royalty free RTL design," the team pledges. "Because RVSoC is a computer system that supports Linux and uses a small amount of hardware resources, it can be applied to various purposes. A feature of RISC-V is that it has a room for the extended instructions by computer system developers. The ability of extension can be the basic requirement for application-specific accelerators and it enables to implement more specialised instruction sets.

性能相當于i386和i486之間的處理器

"The resource-saving of RVSoC can be suitable for the implementation of various accelerators and special processor cores by adding unique instructions, and the development of related software.The number of lines in Verilog HDL code of RVSoC is about 5,000, and it is relatively easy to understand the entire implementation of the Linux capable computer system. Therefore, it is suitable to be used as a sample computer system of the education on computer science."

關于該處理器的詳細技術文章介紹，點擊左下角的“閱讀原文”。

要了解更多的關于RISC V在FPGA上的移植和嵌入式應用，可以參考硬禾學堂聯合清華大學出版社推出的“基于FPGA與RISC-V的嵌入式系統設計”教程，本書作者為RISCV基金會發起的Soft CPU 2019年度的冠軍。

與50位技術專家面對面20年技術見證，附贈技術全景圖

總結

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