【STM32】SPI相关函数和类型
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【STM32】SPI相关函数和类型
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00. 目錄
文章目錄
- 00. 目錄
- 01. SPI簡介
- 02. 相關(guān)類型
- 03. 相關(guān)函數(shù)
- 04. 結(jié)構(gòu)體封裝
- 05. 預(yù)留
- 06. 附錄
- 07. 聲明
01. SPI簡介
SPI 是英語 Serial Peripheral interface 的縮寫，顧名思義就是串行外圍設(shè)備接口。是 Motorola首先在其 MC68HCXX 系列處理器上定義的。SPI 接口主要應(yīng)用在 EEPROM，FLASH，實時時鐘，AD 轉(zhuǎn)換器，還有數(shù)字信號處理器和數(shù)字信號解碼器之間。SPI，是一種高速的，全雙工，同步的通信總線，并且在芯片的管腳上只占用四根線，節(jié)約了芯片的管腳，同時為 PCB 的布局上節(jié)省空間，提供方便，正是出于這種簡單易用的特性，現(xiàn)在越來越多的芯片集成了這種通信協(xié)議，STM32F4 也有 SPI 接口。
02. 相關(guān)類型
SPI Init structure definition
/** * @brief SPI Init structure definition */typedef struct {uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.This parameter can be a value of @ref SPI_data_direction */uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.This parameter can be a value of @ref SPI_mode */uint16_t SPI_DataSize; /*!< Specifies the SPI data size.This parameter can be a value of @ref SPI_data_size */uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.This parameter can be a value of @ref SPI_Clock_Polarity */uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.This parameter can be a value of @ref SPI_Clock_Phase */uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed byhardware (NSS pin) or by software using the SSI bit.This parameter can be a value of @ref SPI_Slave_Select_management */uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will beused to configure the transmit and receive SCK clock.This parameter can be a value of @ref SPI_BaudRate_Prescaler@note The communication clock is derived from the masterclock. The slave clock does not need to be set. */uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.This parameter can be a value of @ref SPI_MSB_LSB_transmission */uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ }SPI_InitTypeDef;I2S Init structure definition
/** * @brief I2S Init structure definition */typedef struct {uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.This parameter can be a value of @ref I2S_Mode */uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.This parameter can be a value of @ref I2S_Standard */uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.This parameter can be a value of @ref I2S_Data_Format */uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.This parameter can be a value of @ref I2S_MCLK_Output */uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.This parameter can be a value of @ref I2S_Audio_Frequency */uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.This parameter can be a value of @ref I2S_Clock_Polarity */ }I2S_InitTypeDef;SPI_Exported_Constants
/** @defgroup SPI_Exported_Constants* @{*/#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \((PERIPH) == SPI2) || \((PERIPH) == SPI3) || \((PERIPH) == SPI4) || \((PERIPH) == SPI5) || \((PERIPH) == SPI6))#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \((PERIPH) == SPI2) || \((PERIPH) == SPI3) || \((PERIPH) == SPI4) || \((PERIPH) == SPI5) || \((PERIPH) == SPI6) || \((PERIPH) == I2S2ext) || \((PERIPH) == I2S3ext))#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \((PERIPH) == SPI3))#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \((PERIPH) == SPI3) || \((PERIPH) == I2S2ext) || \((PERIPH) == I2S3ext))#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \((PERIPH) == I2S3ext))SPI_data_direction
/** @defgroup SPI_data_direction * @{*/#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \((MODE) == SPI_Direction_2Lines_RxOnly) || \((MODE) == SPI_Direction_1Line_Rx) || \((MODE) == SPI_Direction_1Line_Tx))SPI_mode
/** @defgroup SPI_mode * @{*/#define SPI_Mode_Master ((uint16_t)0x0104) #define SPI_Mode_Slave ((uint16_t)0x0000) #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \((MODE) == SPI_Mode_Slave))SPI_data_size
/** @defgroup SPI_data_size * @{*/#define SPI_DataSize_16b ((uint16_t)0x0800) #define SPI_DataSize_8b ((uint16_t)0x0000) #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \((DATASIZE) == SPI_DataSize_8b))SPI_Clock_Polarity
/** @defgroup SPI_Clock_Polarity * @{*/#define SPI_CPOL_Low ((uint16_t)0x0000) #define SPI_CPOL_High ((uint16_t)0x0002) #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \((CPOL) == SPI_CPOL_High))SPI_Clock_Phase
/** @defgroup SPI_Clock_Phase * @{*/#define SPI_CPHA_1Edge ((uint16_t)0x0000) #define SPI_CPHA_2Edge ((uint16_t)0x0001) #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \((CPHA) == SPI_CPHA_2Edge))SPI_Slave_Select_management
/** @defgroup SPI_Slave_Select_management * @{*/#define SPI_NSS_Soft ((uint16_t)0x0200) #define SPI_NSS_Hard ((uint16_t)0x0000) #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \((NSS) == SPI_NSS_Hard))SPI_BaudRate_Prescaler
/** @defgroup SPI_BaudRate_Prescaler * @{*/#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \((PRESCALER) == SPI_BaudRatePrescaler_4) || \((PRESCALER) == SPI_BaudRatePrescaler_8) || \((PRESCALER) == SPI_BaudRatePrescaler_16) || \((PRESCALER) == SPI_BaudRatePrescaler_32) || \((PRESCALER) == SPI_BaudRatePrescaler_64) || \((PRESCALER) == SPI_BaudRatePrescaler_128) || \((PRESCALER) == SPI_BaudRatePrescaler_256))SPI_MSB_LSB_transmission
/** @defgroup SPI_MSB_LSB_transmission * @{*/#define SPI_FirstBit_MSB ((uint16_t)0x0000) #define SPI_FirstBit_LSB ((uint16_t)0x0080) #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \((BIT) == SPI_FirstBit_LSB))SPI_I2S_Mode
/** @defgroup SPI_I2S_Mode * @{*/#define I2S_Mode_SlaveTx ((uint16_t)0x0000) #define I2S_Mode_SlaveRx ((uint16_t)0x0100) #define I2S_Mode_MasterTx ((uint16_t)0x0200) #define I2S_Mode_MasterRx ((uint16_t)0x0300) #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \((MODE) == I2S_Mode_SlaveRx) || \((MODE) == I2S_Mode_MasterTx)|| \((MODE) == I2S_Mode_MasterRx))SPI_I2S_Standard
/** @defgroup SPI_I2S_Standard * @{*/#define I2S_Standard_Phillips ((uint16_t)0x0000) #define I2S_Standard_MSB ((uint16_t)0x0010) #define I2S_Standard_LSB ((uint16_t)0x0020) #define I2S_Standard_PCMShort ((uint16_t)0x0030) #define I2S_Standard_PCMLong ((uint16_t)0x00B0) #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \((STANDARD) == I2S_Standard_MSB) || \((STANDARD) == I2S_Standard_LSB) || \((STANDARD) == I2S_Standard_PCMShort) || \((STANDARD) == I2S_Standard_PCMLong))SPI_I2S_Data_Format
/** @defgroup SPI_I2S_Data_Format * @{*/#define I2S_DataFormat_16b ((uint16_t)0x0000) #define I2S_DataFormat_16bextended ((uint16_t)0x0001) #define I2S_DataFormat_24b ((uint16_t)0x0003) #define I2S_DataFormat_32b ((uint16_t)0x0005) #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \((FORMAT) == I2S_DataFormat_16bextended) || \((FORMAT) == I2S_DataFormat_24b) || \((FORMAT) == I2S_DataFormat_32b))SPI_I2S_MCLK_Output
/** @defgroup SPI_I2S_MCLK_Output * @{*/#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \((OUTPUT) == I2S_MCLKOutput_Disable))SPI_I2S_Audio_Frequency
/** @defgroup SPI_I2S_Audio_Frequency * @{*/#define I2S_AudioFreq_192k ((uint32_t)192000) #define I2S_AudioFreq_96k ((uint32_t)96000) #define I2S_AudioFreq_48k ((uint32_t)48000) #define I2S_AudioFreq_44k ((uint32_t)44100) #define I2S_AudioFreq_32k ((uint32_t)32000) #define I2S_AudioFreq_22k ((uint32_t)22050) #define I2S_AudioFreq_16k ((uint32_t)16000) #define I2S_AudioFreq_11k ((uint32_t)11025) #define I2S_AudioFreq_8k ((uint32_t)8000) #define I2S_AudioFreq_Default ((uint32_t)2)#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \((FREQ) <= I2S_AudioFreq_192k)) || \((FREQ) == I2S_AudioFreq_Default))SPI_I2S_Clock_Polarity
/** @defgroup SPI_I2S_Clock_Polarity * @{*/#define I2S_CPOL_Low ((uint16_t)0x0000) #define I2S_CPOL_High ((uint16_t)0x0008) #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \((CPOL) == I2S_CPOL_High))SPI_I2S_DMA_transfer_requests
/** @defgroup SPI_I2S_DMA_transfer_requests * @{*/#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))SPI_NSS_internal_software_management
/** @defgroup SPI_NSS_internal_software_management * @{*/#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \((INTERNAL) == SPI_NSSInternalSoft_Reset))SPI_CRC_Transmit_Receive
/** @defgroup SPI_CRC_Transmit_Receive * @{*/#define SPI_CRC_Tx ((uint8_t)0x00) #define SPI_CRC_Rx ((uint8_t)0x01) #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))SPI_direction_transmit_receive
/** @defgroup SPI_direction_transmit_receive * @{*/#define SPI_Direction_Rx ((uint16_t)0xBFFF) #define SPI_Direction_Tx ((uint16_t)0x4000) #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \((DIRECTION) == SPI_Direction_Tx))SPI_I2S_interrupts_definition
/** @defgroup SPI_I2S_interrupts_definition * @{*/#define SPI_I2S_IT_TXE ((uint8_t)0x71) #define SPI_I2S_IT_RXNE ((uint8_t)0x60) #define SPI_I2S_IT_ERR ((uint8_t)0x50) #define I2S_IT_UDR ((uint8_t)0x53) #define SPI_I2S_IT_TIFRFE ((uint8_t)0x58)#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \((IT) == SPI_I2S_IT_RXNE) || \((IT) == SPI_I2S_IT_ERR))#define SPI_I2S_IT_OVR ((uint8_t)0x56) #define SPI_IT_MODF ((uint8_t)0x55) #define SPI_IT_CRCERR ((uint8_t)0x54)#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\((IT) == SPI_I2S_IT_TIFRFE))SPI_I2S_flags_definition
/** @defgroup SPI_I2S_flags_definition * @{*/#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) #define I2S_FLAG_UDR ((uint16_t)0x0008) #define SPI_FLAG_CRCERR ((uint16_t)0x0010) #define SPI_FLAG_MODF ((uint16_t)0x0020) #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) #define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100)#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \((FLAG) == SPI_I2S_FLAG_TIFRFE))03. 相關(guān)函數(shù)
/* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the SPI configuration to the default reset state *****/ void SPI_I2S_DeInit(SPI_TypeDef* SPIx);/* Initialization and Configuration functions *********************************/ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);/* Data transfers functions ***************************************************/ void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);/* Hardware CRC Calculation functions *****************************************/ void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); void SPI_TransmitCRC(SPI_TypeDef* SPIx); uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);/* DMA transfers management functions *****************************************/ void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);/* Interrupts and flags management functions **********************************/ void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);04. 結(jié)構(gòu)體封裝
/** * @brief Serial Peripheral Interface*/typedef struct {__IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */uint16_t RESERVED0; /*!< Reserved, 0x02 */__IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */uint16_t RESERVED1; /*!< Reserved, 0x06 */__IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */uint16_t RESERVED2; /*!< Reserved, 0x0A */__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */uint16_t RESERVED3; /*!< Reserved, 0x0E */__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */uint16_t RESERVED4; /*!< Reserved, 0x12 */__IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */uint16_t RESERVED5; /*!< Reserved, 0x16 */__IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */uint16_t RESERVED6; /*!< Reserved, 0x1A */__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */uint16_t RESERVED7; /*!< Reserved, 0x1E */__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */uint16_t RESERVED8; /*!< Reserved, 0x22 */ } SPI_TypeDef;05. 預(yù)留
06. 附錄
6.1 【STM32】STM32系列教程匯總
網(wǎng)址：【STM32】STM32系列教程匯總
07. 聲明
總結(jié)
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