ENTRY(relocate_code)mov r4, r0 /* save addr_sp */mov r5, r1 /* save addr of gd */mov r6, r2 /* save addr of destination *///用戶添加，跳轉到board_init_r函數執行mov sp, r4 mov r0, r5 mov r1, r6 bl board_init_r//用戶添加，跳轉到board_init_r函數執行 #if 0/* Set up the stack */ stack_setup:mov sp, r4adr r0, _startcmp r0, r6moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */beq clear_bss /* skip relocation */mov r1, r6 /* r1 <- scratch for copy_loop */ldr r3, _image_copy_end_ofsadd r2, r0, r3 /* r2 <- source end address */copy_loop:ldmia r0!, {r9-r10} /* copy from source address [r0] */stmia r1!, {r9-r10} /* copy to target address [r1] */cmp r0, r2 /* until source end address [r2] */blo copy_loop/** fix .rel.dyn relocations*/ldr r0, _TEXT_BASE /* r0 <- Text base */sub r9, r6, r0 /* r9 <- relocation offset */ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */add r10, r10, r0 /* r10 <- sym table in FLASH */ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ fixloop:ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */add r0, r0, r9 /* r0 <- location to fix up in RAM */ldr r1, [r2, #4]and r7, r1, #0xffcmp r7, #23 /* relative fixup? */beq fixrelcmp r7, #2 /* absolute fixup? */beq fixabs/* ignore unknown type of fixup */b fixnext fixabs:/* absolute fix: set location to (offset) symbol value */mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */add r1, r10, r1 /* r1 <- address of symbol in table */ldr r1, [r1, #4] /* r1 <- symbol value */add r1, r1, r9 /* r1 <- relocated sym addr */b fixnext fixrel:/* relative fix: increase location by offset */ldr r1, [r0]add r1, r1, r9 fixnext:str r1, [r0]add r2, r2, #8 /* each rel.dyn entry is 8 bytes */cmp r2, r3blo fixloopb clear_bss _rel_dyn_start_ofs:.word __rel_dyn_start - _start _rel_dyn_end_ofs:.word __rel_dyn_end - _start _dynsym_start_ofs:.word __dynsym_start - _startclear_bss:ldr r0, _bss_start_ofsldr r1, _bss_end_ofsmov r4, r6 /* reloc addr */add r0, r0, r4add r1, r1, r4mov r2, #0x00000000 /* clear */clbss_l:cmp r0, r1 /* clear loop... */bhs clbss_e /* if reached end of bss, exit */str r2, [r0]add r0, r0, #4b clbss_l clbss_e:/** We are done. Do not return, instead branch to second part of board* initialization, now running from RAM.*/ jump_2_ram: /** If I-cache is enabled invalidate it*/ #ifndef CONFIG_SYS_ICACHE_OFFmcr p15, 0, r0, c7, c5, 0 @ invalidate icachemcr p15, 0, r0, c7, c10, 4 @ DSBmcr p15, 0, r0, c7, c5, 4 @ ISB #endif /** Move vector table*/ #if !defined(CONFIG_TEGRA20)/* Set vector address in CP15 VBAR register */ldr r0, =_startadd r0, r0, r9mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif /* !Tegra20 */ldr r0, _board_init_r_ofsadr r1, _startadd lr, r0, r1add lr, lr, r9/* setup parameters for board_init_r */mov r0, r5 /* gd_t */mov r1, r6 /* dest_addr *//* jump to it ... */mov pc, lr_board_init_r_ofs:.word board_init_r - _start #endif ENDPROC(relocate_code) #endif

/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ //#define CONFIG_NR_DRAM_BANKS 1 //#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ //#define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */ /* SMDKC100 has 2 banks of DRAM */ #define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */ #define SDRAM_BANK_SIZE 0x10000000 /* 256 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
void dram_init_banksize(void) {/*gd->bd->bi_dram[0].start = PHYS_SDRAM_1;gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;*/gd->bd->bi_dram[0].start = PHYS_SDRAM_1;gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;gd->bd->bi_dram[1].start = PHYS_SDRAM_2;gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; }
int dram_init(void) {//gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE;return 0; }
int board_init(void) {//smc9115_pre_init();gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;return 0; }
int checkboard(void) {printf("Board:\treal210\n");return 0; }

//#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR + 0x10000000)
//#define CONFIG_SYS_PROMPT "SMDKC100 # " #define CONFIG_SYS_PROMPT "REAL210 # "
//#define CONFIG_SERIAL0 1 /* use SERIAL 0 on SMDKC100 */ #define CONFIG_SERIAL2 1 /* use SERIAL 2 on REAL210 */
//#define CONFIG_IDENT_STRING " for SMDKC100" #define CONFIG_IDENT_STRING " for REAL210"
CONFIG_SYS_TEXT_BASE = 0x33e00000
//#define CONFIG_ENV_IS_IN_ONENAND 1 #define CONFIG_ENV_IS_NOWHERE 1
//#define CONFIG_CMD_ONENAND #undef CONFIG_CMD_ONENAND
reset: clear_bss://BSS清除，由用戶添加ldr r0, =__bss_startldr r1, =__bss_end__mov r2, #0x0 clbss_l:str r2, [r0],#4cmp r0, r1bne clbss_l//BSS清除，由用戶添加bl save_boot_params/** set the cpu to SVC32 mode*/mrs r0, cpsrbic r0, r0, #0x1forr r0, r0, #0xd3msr cpsr,r0/** Setup vector:* (OMAP4 spl TEXT_BASE is not 32 byte aligned.* Continue to use ROM code vector only in OMAP4 spl)*/ #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Registerbic r0, #CR_V @ V = 0mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register/* Set vector address in CP15 VBAR register */ldr r0, =_startmcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif/* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INITbl cpu_ini _cp15bl cpu_init_crit #endif

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