Abstract

　　本實驗實現了對SRAM每一個地址進行遍歷讀/寫操作，然后對比讀寫前后的數據是否一致，最后通過一個LED燈的亮滅進行指示；

Introduction

　　DE2-115上用的SRAM是IS61WV102416BL(1Mx16 High-Speed Asynchronous CMOS Static RAM With 3.3V Supply)?

　　

　　

　　

　　我們把SRAM_CE,SRAM_OE,SRAM_UB,SRAM_LB置0,這樣寫操作時,只需送數據和地址,同時把SRAM_WE拉低,然后延時Twc時間在把SRAM_WE拉高,這時就把數據寫入相應的地址;讀數據時,只需把需要讀出的地址放到SRAM的地址總線上,然后延遲Taa時間后就可以讀出數據了.

　　SRAM寫時序:

　　

　　SRAM讀時序:

　　

sram_controller.v

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`timescale 1ns/1ps // ********************************************************************* // // Filename: sram_controller.v?????????????????????????????????????????? // // Projects: sram_controller on DE2-115????????????????????????????????? // //?????????? without? external clock???????????????????????????????????? // // Function: check the wirte/read data by led,?????????????????????????? // //?????????? right:LED=1 Wrong:LED=0???????????????????????????????????? //???????????? // Author? : Liu Qiang?????????????????????????????????????????????????? // // Date??? : 2011-11-21????????????????????????????????????????????????? // // Version : 1.0???????????????????????????????????????????????????????? // // Company :???????????????????????????????????????????????????????????? // // ********************************************************************* // ?? module sram_controller( //? intput input clk_50, input rst_n, //? output output[19:0] sram_addr, output sram_wr_n, output sram_ce_n, output sram_oe_n, output sram_ub_n, output sram_lb_n, output led, //? inout inout[15:0] sram_data ); // assign sram_ce_n = 1'b0;??? //sram chip select always enable assign sram_oe_n = 1'b0;??? //sram output always enable assign sram_ub_n = 1'b0;??? //upper byte always available assign sram_lb_n = 1'b0;??? //lower byte always available // reg[25:0] delay;??????? //延時計數器,周期約為1.34s always@(posedge clk_50 or negedge rst_n) ????if(!rst_n) ????????delay <= 26'd0; ????else ????????delay <= delay+1'b1; // reg[15:0] wr_data; reg[15:0] rd_data; reg[19:0] addr_r; wire sram_wr_req; wire sram_rd_req; reg led_r; ?? assign sram_wr_req = (delay == 26'd9999); assign sram_rd_req = (delay == 26'd19999); ?? always@(posedge clk_50 or negedge rst_n) ????if(!rst_n) ????????wr_data <= 16'b0; ????else if(delay == 26'd29999) ????????wr_data <= wr_data+1'b1; ?????????? always@(posedge clk_50 or negedge rst_n) ????if(!rst_n) ????????addr_r <= 20'b0; ????else if(delay == 26'd29999) ????????addr_r <= addr_r+1'b1; ?????? always@(posedge clk_50 or negedge rst_n) ????????if(!rst_n) ????????????led_r <= 1'b0; ????????else if(delay == 26'd29999) ????????????begin ????????????????if(wr_data == rd_data) ????????????????????led_r <= 1'b1; ????????????????else ????????????????????led_r <= 1'b0; ????????????end assign led = led_r; // `define DELAY_80NS? (cnt == 3'd7)?? //80nss取決于Twc的值, cnt=7約140ns; ?? reg[3:0] cstate, nstate; parameter?? IDEL = 4'd0, ????????????WRT0 = 4'd1, ????????????WRT1 = 4'd2, ????????????REA0 = 4'd3, ????????????REA1 = 4'd4; ?????????????? reg[2:0] cnt; always@(posedge clk_50 or negedge rst_n) ????if(!rst_n) ????????cnt <= 3'b0; ????else if(cstate == IDEL) ????????cnt <= 3'b0; ????else ????????cnt <= cnt+1'b1; //? 兩段式狀態機寫法，時序邏輯??????? always@(posedge clk_50 or negedge rst_n) ????if(!rst_n) ????????cstate <= IDEL; ????else ????????cstate <= nstate; //? 兩段式狀態機寫法，組合邏輯??????????? always@(posedge clk_50 or negedge rst_n) ????case(cstate) ????????IDEL:?? if(sram_wr_req) ????????????????????nstate <= WRT0; ????????????????else if(sram_rd_req) ????????????????????nstate <= REA0; ????????????????else ????????????????????nstate <= IDEL; ????????WRT0:?? if(`DELAY_80NS) ????????????????????nstate <= WRT1; ????????????????else ????????????????????nstate <= WRT0; ????????WRT1:?? nstate <= IDEL; ????????REA0:?? if(`DELAY_80NS) ????????????????????nstate <= REA1; ????????????????else ????????????????????nstate <= REA0; ????????REA1:?? nstate <= IDEL; ????????default:nstate <= IDEL; ????endcase ?????? assign sram_addr =addr_r; //? 鎖存數據 reg sdlink;???? //SRAM地址總線控制信號 always@(posedge clk_50 or negedge rst_n) ????if(!rst_n) ????????rd_data <= 16'b0; ????else if(cstate == REA1) ????????rd_data <= sram_data; ?????????? always@(posedge clk_50 or negedge rst_n) ????if(!rst_n) ????????sdlink <= 1'b0; ????else ????????case(cstate) ????????????IDEL:?? if(sram_wr_req) ????????????????????????sdlink <= 1'b1; ????????????????????else if(sram_rd_req) ????????????????????????sdlink <= 1'b0; ????????????????????else? ????????????????????????sdlink <= 1'b0; ????????????WRT0:?? sdlink <= 1'b1; ????????????default:sdlink <= 1'b0; ????????endcase ?????? assign sram_data = sdlink ? wr_data:16'hzzzz; assign sram_wr_n = ~sdlink; ?? endmodule

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