文章來(lái)源為noraml matloff教授寫(xiě)的Major Componets of Computer "Engine",文章有點(diǎn)老,意義還是有的:-)

History of Intel CPU Structure

The earliest widely-used Intel processor chip was the 8080. Its word size was 8 bits, and it included registers
named A, B, C and D (and a couple of others). Address size was 16 bits.
The next series of Intel chips, the 8086/8088,and then the 80286, featured 16-bit words and 20-bit addresses.
The A, B, C and D registers were accordingly extended to 16-bit size and renamed AX, BX, CX
and DX (‘X’ stood for “extended”). Other miscellaneous registers were added. The lower byte of AX was
called AL, the higher byte AH, and similarly for BL, BH, etc.
??? ??
??? ??? 最早被廣泛應(yīng)用的Intel處理器是8080.它的字長(zhǎng)為8,包括A,B,C,D(還有一些其他的)寄存器,地址長(zhǎng)度為16位。接下來(lái)的Intel芯片是8086/8080，然后是80286，擁有16位的字長(zhǎng)和20位的地址長(zhǎng)度。A,B,C,D寄存器也相應(yīng)的擴(kuò)展到16位長(zhǎng)，并被命名為AX,BX,CX,DX('X'代表"擴(kuò)展的")。一些各種功能的寄存器也增加了。AX的低位被稱(chēng)作AL，高位作為AH，BL，BH等也一樣。

Beginning with the 80386 and extending to the Pentium series, both word and address size has been 32 bits.
The registers were again extended in size, to 32 bits, and renamed EAX, EBX and so on (‘E’ for “extended”).
The pre-32-bit Intel CPUs, starting with 8086/8088, replaced the single register PC with a pair of registers,
CS (for code segment) and IP (for instruction pointer). A rough description is that the CS register pointed to
the code segment, which is the place in memory where the program’s instructions start, and the IP register
then specified the distance in bytes from that starting point to the current instruction. Thus by combining
the information given in c(CS) and c(IP), we obtained the absolute address of the current instruction.

??? ?? 從80386開(kāi)始到奔騰系列，字長(zhǎng)和地址長(zhǎng)度都變成了32位，寄存器也再次擴(kuò)展到32位，并被稱(chēng)為EAX，EBX('E'代表"擴(kuò)展的")。在32位之前的Intel CPU，從8086/8088開(kāi)始，把單個(gè)PC寄存器用一對(duì)寄存器取代，CS(代碼段)和IP(指令指針)。一個(gè)粗糙的描述就是CS寄存器指向代碼段，也就是內(nèi)存中程序指令開(kāi)始執(zhí)行的地方，IP寄存器接著指定用字節(jié)表示的從當(dāng)前指令到起始點(diǎn)的距離。這樣通過(guò)兩者結(jié)合，我們可以得到當(dāng)前指令的絕對(duì)地址。

This is still true today when an Intel CPU runs in in 16-bit mode, in which case it generates 20-bit addresses.
The CS register is only 16 bits, but it represents a 20-bit address whose least significant four bits are implicitly
0s. (This implies that code segments are allowed to begin only at addresses which are multiples of 16.)
The CPU generates the address of the current instruction by concatenating c(CS) with four 0 bits and then
adding the result to c(IP).

??? ?? 這在今天看來(lái)也仍是正確的，如果Intel CPU運(yùn)行在16位模式，在這種情況下，它產(chǎn)生20位的地址。CS寄存器只有十六位，但它確表示二十位的地址，這就暗示地址的最低4位為'0'。(這表示代碼段只能在16的倍數(shù)的地址上開(kāi)始)。CPU通過(guò)在CS上添加4個(gè)'0'位再加上IP的值來(lái)取得當(dāng)前的指令地址。

Suppose for example the current instruction is located at 0x21082, and the code segment begins at 0x21040.
Then c(CS) and c(IP) will be 0x2104 and 0x0042, respectively, and when the instruction is to be executed,
its address will be generated by combining these two values as shown above.

??? ?? 假設(shè)當(dāng)前的指令地位為0x21082，代碼段從0x21040開(kāi)始，那么CS和IP就應(yīng)該分別為0x2104和0x0042。當(dāng)指令被執(zhí)行時(shí)，它的地址就上面的兩個(gè)值相加得到。

The situation is similar for stacks and data. For example, instead of having a single SP register as in our
model of a typical CPU above, the earlier Intel CPUs (and current CPUs when they are running in 16-bit
mode) use a pair of registers, SS and SP. SS specifies the start of the stack segment, and SP contains the
distance from there to the current top-of-stack. For data, the DS register points to the start of the data
segment, and a 16-bit value contained in the instruction specifies the distance from there to the desired data
item.

??? ?? 棧和數(shù)據(jù)的情況也類(lèi)似。例如，早期的Intel CPUs(和運(yùn)行在16位模式的現(xiàn)在的CPUs)使用一對(duì)寄存器，SS和SP，而不是向上面典型的CPU那樣只用單個(gè)的SP寄存器。SS指定棧段的開(kāi)始，SP包含從那里到棧頂?shù)木嚯x。對(duì)于數(shù)據(jù)來(lái)說(shuō)，DS寄存器指向數(shù)據(jù)段的開(kāi)始，指令中的一個(gè)16位的值指定到需要的數(shù)據(jù)項(xiàng)的距離。

Since IP, SP and the data-item distance specified within an instruction are all 16-bit quantities, it follows
that the code, stack and data segments are limited to 2¹⁶= 65, 536 bytes in size. This can make things quite
inconvenient for the programmer. If, for instance, we have an array of length, say, 100,000 bytes, we could
not fit the array into one data segment. We would need two such segments, and the programmer would have
to include in the program lines of code which change the value of c(DS) whenever it needs to access a part
of the array in the other data segment.

??? ?? 由于IP，SP以及指令中指定的數(shù)據(jù)的距離都是16位的值，這就使得代碼段，棧段和數(shù)據(jù)段的長(zhǎng)度都被限制在2¹⁶= 65,536位。這樣對(duì)程序員來(lái)說(shuō)很不方便。比如，如果我們有個(gè)數(shù)組的長(zhǎng)度為，假如100,000byte，我們就不能把它放入一個(gè)數(shù)據(jù)段中。我們需要兩個(gè)這樣的段，而且當(dāng)程序員需要訪問(wèn)在另一個(gè)段中的數(shù)組時(shí)，需要在代碼行中放入改變DS值的代碼。

These problems are avoided by the newer operating systems which run on Intel machines today, such as
Windows and Linux, since they run in 32-bit mode. Addresses are also of size 32 bits in that mode, and IP,
SP and data-item distance are 32 bits as well. Thus a code segment, for instance, can fill all of memory, and
segment switching as illustrated above is unnecessary.

??? ?? 今天這些問(wèn)題被運(yùn)行在Intel機(jī)器上的新的操作系統(tǒng)避免了，例如Windows和Linux，由于他們運(yùn)行在32位模式。這種模式下地址也是32位的，IP，SP和數(shù)據(jù)距離也同樣。這樣一個(gè)代碼段可以填滿整個(gè)內(nèi)存，而且像上面那樣的段切換也不再需要了。

發(fā)現(xiàn)這一段的意思不是太大，不過(guò)還是堅(jiān)持翻完了
時(shí)間也花了一個(gè)多小時(shí)，還是看快。

轉(zhuǎn)載于:https://www.cnblogs.com/denovo/archive/2006/08/21/482724.html

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