static void SetSysClockTo72(void)的一些理解
static void SetSysClockTo72(void)
{
??__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
??
??/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ ???
??/* Enable HSE */ ???
??RCC->CR |= ((uint32_t)RCC_CR_HSEON);//打開HSE
?
??/* Wait till HSE is ready and if Time out is reached exit */
??do
??{
????HSEStatus = RCC->CR & RCC_CR_HSERDY;
????StartUpCounter++; ?
??} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));//等待HSE就緒
?
??if ((RCC->CR & RCC_CR_HSERDY) != RESET)
??{
????HSEStatus = (uint32_t)0x01;
??}
??else
??{
????HSEStatus = (uint32_t)0x00;
??} ?
?
??if (HSEStatus == (uint32_t)0x01)
??{
????/* Enable Prefetch Buffer */
????FLASH->ACR |= FLASH_ACR_PRFTBE;
?
????/* Flash 2 wait state */
????FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
????FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; ???//先不管
?
?
????/* HCLK = SYSCLK */
????RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
??????
????/*?PCLK2?= HCLK */
????RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
????
????/* PCLK1?= HCLK /2*/
????RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;//設置三個時鐘的分頻系數,確定其和系統時鐘的關系
?
#ifdef STM32F10X_CL
????/* Configure PLLs ------------------------------------------------------*/
????/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
????/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
????????
????RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
??????????????????????????????RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
????RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
?????????????????????????????RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
??
????/* Enable PLL2 */
????RCC->CR |= RCC_CR_PLL2ON;
????/* Wait till PLL2 is ready */
????while((RCC->CR & RCC_CR_PLL2RDY) == 0)
????{
????}
????
???
????/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
????RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
????RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
????????????????????????????RCC_CFGR_PLLMULL9); //確定PLL的倍頻系數和時鐘來源
#else ???
????/* ?PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
????RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
????????????????????????????????????????RCC_CFGR_PLLMULL));//將PLLSRC，PLLXTPRE，PLLMULL對應的位置零
????RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);// 或符號”|”是前后兩種狀態同時取的意思
#endif /* STM32F10X_CL */
?
????/* Enable PLL */
????RCC->CR |= RCC_CR_PLLON;//PLL時鐘打開
?
????/* Wait till PLL is ready */
????while((RCC->CR & RCC_CR_PLLRDY) == 0)
????{
????}
????
????/* Select PLL as system clock source */
????RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
????RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;//將PLL作為系統時鐘來源????
?
????/* Wait till PLL is used as system clock source */
????while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
????{
????}
??}
??else
??{ /* If HSE fails to start-up, the application will have wrong clock
?????????configuration. User can add here some code to deal with this error */
??}
}
#endif
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