一、實驗目的

（1）學習并掌握Quartus II的使用方法
（2）學習簡單時序電路的設計和硬件測試。
（3）學習使用VHDL 語言方法進行邏輯設計輸入
（4）學習設計8位16進制頻率計,學習較復雜的數字系統設計方法，并在實驗開發系統上熟悉運行輸入及仿真步驟原理

二、實驗儀器設備

（1） PC機一臺。
（2）Quartus Ⅱ開發軟件一套
（3）EDA實驗開發系統一套(EP1C12Q240C8)

三、實驗原理

頻率計的工作原理是用一個頻率穩定度高的頻率源作為基準時鐘,對比測量其他信號的頻率,也就是周期性信號在單位時間內變化的次數。
頻率計原理如圖所示

#mermaid-svg-ITt1RP1dilxFj5xt .label{font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family);fill:#333;color:#333}#mermaid-svg-ITt1RP1dilxFj5xt .label text{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt .node rect,#mermaid-svg-ITt1RP1dilxFj5xt .node circle,#mermaid-svg-ITt1RP1dilxFj5xt .node ellipse,#mermaid-svg-ITt1RP1dilxFj5xt .node polygon,#mermaid-svg-ITt1RP1dilxFj5xt .node path{fill:#ECECFF;stroke:#9370db;stroke-width:1px}#mermaid-svg-ITt1RP1dilxFj5xt .node .label{text-align:center;fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt .node.clickable{cursor:pointer}#mermaid-svg-ITt1RP1dilxFj5xt .arrowheadPath{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt .edgePath .path{stroke:#333;stroke-width:1.5px}#mermaid-svg-ITt1RP1dilxFj5xt .flowchart-link{stroke:#333;fill:none}#mermaid-svg-ITt1RP1dilxFj5xt .edgeLabel{background-color:#e8e8e8;text-align:center}#mermaid-svg-ITt1RP1dilxFj5xt .edgeLabel rect{opacity:0.9}#mermaid-svg-ITt1RP1dilxFj5xt .edgeLabel span{color:#333}#mermaid-svg-ITt1RP1dilxFj5xt .cluster rect{fill:#ffffde;stroke:#aa3;stroke-width:1px}#mermaid-svg-ITt1RP1dilxFj5xt .cluster text{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt div.mermaidTooltip{position:absolute;text-align:center;max-width:200px;padding:2px;font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family);font-size:12px;background:#ffffde;border:1px solid #aa3;border-radius:2px;pointer-events:none;z-index:100}#mermaid-svg-ITt1RP1dilxFj5xt .actor{stroke:#ccf;fill:#ECECFF}#mermaid-svg-ITt1RP1dilxFj5xt text.actor>tspan{fill:#000;stroke:none}#mermaid-svg-ITt1RP1dilxFj5xt .actor-line{stroke:grey}#mermaid-svg-ITt1RP1dilxFj5xt .messageLine0{stroke-width:1.5;stroke-dasharray:none;stroke:#333}#mermaid-svg-ITt1RP1dilxFj5xt .messageLine1{stroke-width:1.5;stroke-dasharray:2, 2;stroke:#333}#mermaid-svg-ITt1RP1dilxFj5xt #arrowhead path{fill:#333;stroke:#333}#mermaid-svg-ITt1RP1dilxFj5xt .sequenceNumber{fill:#fff}#mermaid-svg-ITt1RP1dilxFj5xt #sequencenumber{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt #crosshead path{fill:#333;stroke:#333}#mermaid-svg-ITt1RP1dilxFj5xt .messageText{fill:#333;stroke:#333}#mermaid-svg-ITt1RP1dilxFj5xt .labelBox{stroke:#ccf;fill:#ECECFF}#mermaid-svg-ITt1RP1dilxFj5xt .labelText,#mermaid-svg-ITt1RP1dilxFj5xt .labelText>tspan{fill:#000;stroke:none}#mermaid-svg-ITt1RP1dilxFj5xt .loopText,#mermaid-svg-ITt1RP1dilxFj5xt .loopText>tspan{fill:#000;stroke:none}#mermaid-svg-ITt1RP1dilxFj5xt .loopLine{stroke-width:2px;stroke-dasharray:2, 2;stroke:#ccf;fill:#ccf}#mermaid-svg-ITt1RP1dilxFj5xt .note{stroke:#aa3;fill:#fff5ad}#mermaid-svg-ITt1RP1dilxFj5xt .noteText,#mermaid-svg-ITt1RP1dilxFj5xt .noteText>tspan{fill:#000;stroke:none}#mermaid-svg-ITt1RP1dilxFj5xt .activation0{fill:#f4f4f4;stroke:#666}#mermaid-svg-ITt1RP1dilxFj5xt .activation1{fill:#f4f4f4;stroke:#666}#mermaid-svg-ITt1RP1dilxFj5xt .activation2{fill:#f4f4f4;stroke:#666}#mermaid-svg-ITt1RP1dilxFj5xt .mermaid-main-font{font-family:"trebuchet ms", verdana, arial;font-family:var(--mermaid-font-family)}#mermaid-svg-ITt1RP1dilxFj5xt .section{stroke:none;opacity:0.2}#mermaid-svg-ITt1RP1dilxFj5xt .section0{fill:rgba(102,102,255,0.49)}#mermaid-svg-ITt1RP1dilxFj5xt .section2{fill:#fff400}#mermaid-svg-ITt1RP1dilxFj5xt .section1,#mermaid-svg-ITt1RP1dilxFj5xt .section3{fill:#fff;opacity:0.2}#mermaid-svg-ITt1RP1dilxFj5xt .sectionTitle0{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt .sectionTitle1{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt .sectionTitle2{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt .sectionTitle3{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt .sectionTitle{text-anchor:start;font-size:11px;text-height:14px;font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family)}#mermaid-svg-ITt1RP1dilxFj5xt .grid .tick{stroke:#d3d3d3;opacity:0.8;shape-rendering:crispEdges}#mermaid-svg-ITt1RP1dilxFj5xt .grid .tick text{font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family)}#mermaid-svg-ITt1RP1dilxFj5xt .grid path{stroke-width:0}#mermaid-svg-ITt1RP1dilxFj5xt .today{fill:none;stroke:red;stroke-width:2px}#mermaid-svg-ITt1RP1dilxFj5xt .task{stroke-width:2}#mermaid-svg-ITt1RP1dilxFj5xt .taskText{text-anchor:middle;font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family)}#mermaid-svg-ITt1RP1dilxFj5xt .taskText:not([font-size]){font-size:11px}#mermaid-svg-ITt1RP1dilxFj5xt .taskTextOutsideRight{fill:#000;text-anchor:start;font-size:11px;font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family)}#mermaid-svg-ITt1RP1dilxFj5xt .taskTextOutsideLeft{fill:#000;text-anchor:end;font-size:11px}#mermaid-svg-ITt1RP1dilxFj5xt .task.clickable{cursor:pointer}#mermaid-svg-ITt1RP1dilxFj5xt .taskText.clickable{cursor:pointer;fill:#003163 !important;font-weight:bold}#mermaid-svg-ITt1RP1dilxFj5xt .taskTextOutsideLeft.clickable{cursor:pointer;fill:#003163 !important;font-weight:bold}#mermaid-svg-ITt1RP1dilxFj5xt .taskTextOutsideRight.clickable{cursor:pointer;fill:#003163 !important;font-weight:bold}#mermaid-svg-ITt1RP1dilxFj5xt .taskText0,#mermaid-svg-ITt1RP1dilxFj5xt .taskText1,#mermaid-svg-ITt1RP1dilxFj5xt .taskText2,#mermaid-svg-ITt1RP1dilxFj5xt .taskText3{fill:#fff}#mermaid-svg-ITt1RP1dilxFj5xt .task0,#mermaid-svg-ITt1RP1dilxFj5xt .task1,#mermaid-svg-ITt1RP1dilxFj5xt .task2,#mermaid-svg-ITt1RP1dilxFj5xt .task3{fill:#8a90dd;stroke:#534fbc}#mermaid-svg-ITt1RP1dilxFj5xt .taskTextOutside0,#mermaid-svg-ITt1RP1dilxFj5xt .taskTextOutside2{fill:#000}#mermaid-svg-ITt1RP1dilxFj5xt .taskTextOutside1,#mermaid-svg-ITt1RP1dilxFj5xt .taskTextOutside3{fill:#000}#mermaid-svg-ITt1RP1dilxFj5xt .active0,#mermaid-svg-ITt1RP1dilxFj5xt .active1,#mermaid-svg-ITt1RP1dilxFj5xt .active2,#mermaid-svg-ITt1RP1dilxFj5xt .active3{fill:#bfc7ff;stroke:#534fbc}#mermaid-svg-ITt1RP1dilxFj5xt .activeText0,#mermaid-svg-ITt1RP1dilxFj5xt .activeText1,#mermaid-svg-ITt1RP1dilxFj5xt .activeText2,#mermaid-svg-ITt1RP1dilxFj5xt .activeText3{fill:#000 !important}#mermaid-svg-ITt1RP1dilxFj5xt .done0,#mermaid-svg-ITt1RP1dilxFj5xt .done1,#mermaid-svg-ITt1RP1dilxFj5xt .done2,#mermaid-svg-ITt1RP1dilxFj5xt .done3{stroke:grey;fill:#d3d3d3;stroke-width:2}#mermaid-svg-ITt1RP1dilxFj5xt .doneText0,#mermaid-svg-ITt1RP1dilxFj5xt .doneText1,#mermaid-svg-ITt1RP1dilxFj5xt .doneText2,#mermaid-svg-ITt1RP1dilxFj5xt .doneText3{fill:#000 !important}#mermaid-svg-ITt1RP1dilxFj5xt .crit0,#mermaid-svg-ITt1RP1dilxFj5xt .crit1,#mermaid-svg-ITt1RP1dilxFj5xt .crit2,#mermaid-svg-ITt1RP1dilxFj5xt .crit3{stroke:#f88;fill:red;stroke-width:2}#mermaid-svg-ITt1RP1dilxFj5xt .activeCrit0,#mermaid-svg-ITt1RP1dilxFj5xt .activeCrit1,#mermaid-svg-ITt1RP1dilxFj5xt .activeCrit2,#mermaid-svg-ITt1RP1dilxFj5xt .activeCrit3{stroke:#f88;fill:#bfc7ff;stroke-width:2}#mermaid-svg-ITt1RP1dilxFj5xt .doneCrit0,#mermaid-svg-ITt1RP1dilxFj5xt .doneCrit1,#mermaid-svg-ITt1RP1dilxFj5xt .doneCrit2,#mermaid-svg-ITt1RP1dilxFj5xt .doneCrit3{stroke:#f88;fill:#d3d3d3;stroke-width:2;cursor:pointer;shape-rendering:crispEdges}#mermaid-svg-ITt1RP1dilxFj5xt .milestone{transform:rotate(45deg) scale(0.8, 0.8)}#mermaid-svg-ITt1RP1dilxFj5xt .milestoneText{font-style:italic}#mermaid-svg-ITt1RP1dilxFj5xt .doneCritText0,#mermaid-svg-ITt1RP1dilxFj5xt .doneCritText1,#mermaid-svg-ITt1RP1dilxFj5xt .doneCritText2,#mermaid-svg-ITt1RP1dilxFj5xt .doneCritText3{fill:#000 !important}#mermaid-svg-ITt1RP1dilxFj5xt .activeCritText0,#mermaid-svg-ITt1RP1dilxFj5xt .activeCritText1,#mermaid-svg-ITt1RP1dilxFj5xt .activeCritText2,#mermaid-svg-ITt1RP1dilxFj5xt .activeCritText3{fill:#000 !important}#mermaid-svg-ITt1RP1dilxFj5xt .titleText{text-anchor:middle;font-size:18px;fill:#000;font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family)}#mermaid-svg-ITt1RP1dilxFj5xt g.classGroup text{fill:#9370db;stroke:none;font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family);font-size:10px}#mermaid-svg-ITt1RP1dilxFj5xt g.classGroup text .title{font-weight:bolder}#mermaid-svg-ITt1RP1dilxFj5xt g.clickable{cursor:pointer}#mermaid-svg-ITt1RP1dilxFj5xt g.classGroup rect{fill:#ECECFF;stroke:#9370db}#mermaid-svg-ITt1RP1dilxFj5xt g.classGroup line{stroke:#9370db;stroke-width:1}#mermaid-svg-ITt1RP1dilxFj5xt .classLabel .box{stroke:none;stroke-width:0;fill:#ECECFF;opacity:0.5}#mermaid-svg-ITt1RP1dilxFj5xt .classLabel .label{fill:#9370db;font-size:10px}#mermaid-svg-ITt1RP1dilxFj5xt .relation{stroke:#9370db;stroke-width:1;fill:none}#mermaid-svg-ITt1RP1dilxFj5xt .dashed-line{stroke-dasharray:3}#mermaid-svg-ITt1RP1dilxFj5xt #compositionStart{fill:#9370db;stroke:#9370db;stroke-width:1}#mermaid-svg-ITt1RP1dilxFj5xt #compositionEnd{fill:#9370db;stroke:#9370db;stroke-width:1}#mermaid-svg-ITt1RP1dilxFj5xt #aggregationStart{fill:#ECECFF;stroke:#9370db;stroke-width:1}#mermaid-svg-ITt1RP1dilxFj5xt #aggregationEnd{fill:#ECECFF;stroke:#9370db;stroke-width:1}#mermaid-svg-ITt1RP1dilxFj5xt #dependencyStart{fill:#9370db;stroke:#9370db;stroke-width:1}#mermaid-svg-ITt1RP1dilxFj5xt #dependencyEnd{fill:#9370db;stroke:#9370db;stroke-width:1}#mermaid-svg-ITt1RP1dilxFj5xt #extensionStart{fill:#9370db;stroke:#9370db;stroke-width:1}#mermaid-svg-ITt1RP1dilxFj5xt #extensionEnd{fill:#9370db;stroke:#9370db;stroke-width:1}#mermaid-svg-ITt1RP1dilxFj5xt .commit-id,#mermaid-svg-ITt1RP1dilxFj5xt .commit-msg,#mermaid-svg-ITt1RP1dilxFj5xt .branch-label{fill:lightgrey;color:lightgrey;font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family)}#mermaid-svg-ITt1RP1dilxFj5xt .pieTitleText{text-anchor:middle;font-size:25px;fill:#000;font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family)}#mermaid-svg-ITt1RP1dilxFj5xt .slice{font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family)}#mermaid-svg-ITt1RP1dilxFj5xt g.stateGroup text{fill:#9370db;stroke:none;font-size:10px;font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family)}#mermaid-svg-ITt1RP1dilxFj5xt g.stateGroup text{fill:#9370db;fill:#333;stroke:none;font-size:10px}#mermaid-svg-ITt1RP1dilxFj5xt g.statediagram-cluster .cluster-label text{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt g.stateGroup .state-title{font-weight:bolder;fill:#000}#mermaid-svg-ITt1RP1dilxFj5xt g.stateGroup rect{fill:#ECECFF;stroke:#9370db}#mermaid-svg-ITt1RP1dilxFj5xt g.stateGroup line{stroke:#9370db;stroke-width:1}#mermaid-svg-ITt1RP1dilxFj5xt .transition{stroke:#9370db;stroke-width:1;fill:none}#mermaid-svg-ITt1RP1dilxFj5xt .stateGroup .composit{fill:white;border-bottom:1px}#mermaid-svg-ITt1RP1dilxFj5xt .stateGroup .alt-composit{fill:#e0e0e0;border-bottom:1px}#mermaid-svg-ITt1RP1dilxFj5xt .state-note{stroke:#aa3;fill:#fff5ad}#mermaid-svg-ITt1RP1dilxFj5xt .state-note text{fill:black;stroke:none;font-size:10px}#mermaid-svg-ITt1RP1dilxFj5xt .stateLabel .box{stroke:none;stroke-width:0;fill:#ECECFF;opacity:0.7}#mermaid-svg-ITt1RP1dilxFj5xt .edgeLabel text{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt .stateLabel text{fill:#000;font-size:10px;font-weight:bold;font-family:'trebuchet ms', verdana, arial;font-family:var(--mermaid-font-family)}#mermaid-svg-ITt1RP1dilxFj5xt .node circle.state-start{fill:black;stroke:black}#mermaid-svg-ITt1RP1dilxFj5xt .node circle.state-end{fill:black;stroke:white;stroke-width:1.5}#mermaid-svg-ITt1RP1dilxFj5xt #statediagram-barbEnd{fill:#9370db}#mermaid-svg-ITt1RP1dilxFj5xt .statediagram-cluster rect{fill:#ECECFF;stroke:#9370db;stroke-width:1px}#mermaid-svg-ITt1RP1dilxFj5xt .statediagram-cluster rect.outer{rx:5px;ry:5px}#mermaid-svg-ITt1RP1dilxFj5xt .statediagram-state .divider{stroke:#9370db}#mermaid-svg-ITt1RP1dilxFj5xt .statediagram-state .title-state{rx:5px;ry:5px}#mermaid-svg-ITt1RP1dilxFj5xt .statediagram-cluster.statediagram-cluster .inner{fill:white}#mermaid-svg-ITt1RP1dilxFj5xt .statediagram-cluster.statediagram-cluster-alt .inner{fill:#e0e0e0}#mermaid-svg-ITt1RP1dilxFj5xt .statediagram-cluster .inner{rx:0;ry:0}#mermaid-svg-ITt1RP1dilxFj5xt .statediagram-state rect.basic{rx:5px;ry:5px}#mermaid-svg-ITt1RP1dilxFj5xt .statediagram-state rect.divider{stroke-dasharray:10,10;fill:#efefef}#mermaid-svg-ITt1RP1dilxFj5xt .note-edge{stroke-dasharray:5}#mermaid-svg-ITt1RP1dilxFj5xt .statediagram-note rect{fill:#fff5ad;stroke:#aa3;stroke-width:1px;rx:0;ry:0}:root{--mermaid-font-family: '"trebuchet ms", verdana, arial';--mermaid-font-family: "Comic Sans MS", "Comic Sans", cursive}#mermaid-svg-ITt1RP1dilxFj5xt .error-icon{fill:#522}#mermaid-svg-ITt1RP1dilxFj5xt .error-text{fill:#522;stroke:#522}#mermaid-svg-ITt1RP1dilxFj5xt .edge-thickness-normal{stroke-width:2px}#mermaid-svg-ITt1RP1dilxFj5xt .edge-thickness-thick{stroke-width:3.5px}#mermaid-svg-ITt1RP1dilxFj5xt .edge-pattern-solid{stroke-dasharray:0}#mermaid-svg-ITt1RP1dilxFj5xt .edge-pattern-dashed{stroke-dasharray:3}#mermaid-svg-ITt1RP1dilxFj5xt .edge-pattern-dotted{stroke-dasharray:2}#mermaid-svg-ITt1RP1dilxFj5xt .marker{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt .marker.cross{stroke:#333}:root { --mermaid-font-family: "trebuchet ms", verdana, arial;}#mermaid-svg-ITt1RP1dilxFj5xt {color: rgba(0, 0, 0, 0.75);font: ;}被測信號閘門計數器數據處理與顯示基準時鐘門控信號

輸入待測信號經過脈沖形成電路后形成計數的窄脈沖,時基信號發生器產生計數閘門信號,待測信號通過閘門進入計數器計數，即可得到其頻率。若閘門開啟時間為T,待測信號頻率為$f_x$,在閘門時間T內計數器計數值為N，則待測信號頻率為$f_x$=N/T。閘門時間通常取為1s。
根據頻率的定義和頻率測量的基本原理,測定信號的頻率必須有一個脈寬為1s的輸入信號脈沖計數允許的信號;1s計數結束后，計數值被鎖入鎖存器，計數器清0,為下一測頻計數周期做好準備。測頻控制信號可以由一個獨立的發生器來產生根據測頻原理,測頻控制時序如圖所示。設計要求是:FTCTRL 的計數使能信號CNT_EN能產生一個1s 脈寬的周期信號，并對頻率計中的32位二進制計數器COUNTER32B的 ENABL使能端進行同步控制。當CNT_EN高電平時允許計數，低電平時停止計數，并保持其所計的脈沖數。在停止計數期間，首先需要個鎖存信號LOAD的上跳沿將計數收器在前1s的計數值鎖存進鎖存器REG32B 中，并由外部的16進制7段譯碼器譯出，顯示計數值。設置鎖存器的好處是數據顯示穩定，不會由于周期性的清0信號而不斷閃爍。鎖存信號后,必須有一清0信號RST_CNT對計數器進行清零,為下1s的計數操作做好準備。

四、實驗內容

分別仿真測試模塊例1、例2和例3,再結合例4完成頻率計的完整設計和硬件實現,并給出其測頻時序波形及其分析。建議選實驗電路模式5；8個數碼管以16進制形式顯示測頻輸出;待測頻率輸入FIN 由 clock0輸入,頻率可4Hz、256Hz、3Hz、…、50MHz等；1Hz測頻控制信號CLK1Hz可由 clock2輸入（用跳線選1HZ)。注意，這時8個數碼管的測控顯示值是16進制的。

五、實驗步驟

（1）啟動Quartus II建立一個空白工程,然后命名為 FREQTEST.qpf。
（2）新建VHDL 源程序文件FREQTEST.vhd,輸入程序代碼并保存，進行綜合編譯,若編譯過程中發現錯誤，則找出并更正錯誤，直至編譯成功為止。
（3）選擇目標器件并對相應的引腳進行鎖定,在這里所選擇的器件為Altera公司 Cyclone系列的EPIC12Q240C8芯片。將未使用的管腳設置為三態輸入。則找出并更正錯誤,
（4）對該工程文件進行全程編譯處理，若在編譯過程中發現錯誤直至編譯成功為止。接到PC機的打印機并口
（5）拿出 Altera Byte Blaster II下載電纜，并將此電纜的兩端分別接到PC機的打印機并口和實驗箱的JTAG下載口上，打開電源，執行下載命令，把程序下載到 FPGA器件中，觀察數碼管1~8的16進制顯示狀態。
實例代碼：

LIBRARY IEEE; --頻率計頂層文件 USE IEEE.STD_LOGIC_1164.all; ENTITY FREQTEST IS PORT(CLK1HZ:IN STD_LOGIC;FSIN:IN STD_lOGIC;DOUT:OUT STD_LOGIC_VECTOR(31 downto 0)); END; ARCHITECTURE BEHAV OF FREQTEST isCOMPONENT FTCTRLPORT(CLKK: IN STD_LOGIC; --1HZCNT_EN: OUT STD_LOGIC; --計數器時鐘使能RST_CNT:OUT STD_LOGIC; --計數器清零LOAD : OUT STD_LOGIC); --輸出鎖存信號END COMPONENT;COMPONENT COUNTER32BPORT(FIN: IN STD_LOGIC; --時鐘信號ENABL: IN STD_LOGIC; --清零信號CLR : IN STD_LOGIC; --計數使能信號DOUT: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); --計數結果輸出END COMPONENT;COMPONENT REG32BPORT(LK: IN STD_LOGIC;DIN: IN STD_LOGIC_VECTOR(31 downto 0);DOUT: OUT STD_LOGIC_VECTOR(31 downto 0));END COMPONENT;SIGNAl TSTEN1: STD_LOGIC;SIGNAl CLR_CNT1:STD_LOGIC;SIGNAl LOAD1: STD_LOGIC;SIGNAl DTO1: STD_LOGIC_VECTOR(31 DOWNTO 0);SIGNAl CARRY_OUT1:STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN u1: FTCTRL PORT MAP (CLKK=>CLK1HZ,CNT_EN=>TSTEN1,RST_CNT=>CLR_CNT1,LOAD=>LOAD1); --例化 U2: REG32B PORT MAP(LK=>LOAD1,DIN=>DTO1,DOUT=>DOUT); --例化 U3:COUNTER32B PORT MAP(FIN => FSIN,CLR => CLR_CNT1,ENABL=> TSTEN1,DOUT=>DTO1); --例化 END BEHAV; LIBRARY IEEE; --測頻控制電路 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FTCTRL ISPORT (CLKK : IN STD_LOGIC; --1HZCNT_EN :OUT STD_LOGIC; --計數器使能控制RST_CNT:OUT STD_LOGIC; --計數器清零端Load: OUT STD_LOGIC ); --輸出鎖存信號 END FTCTRL; ARCHITECTURE BEHAV OF FTCTRL ISSIGNAL Div2CLK : STD_LOGIC; BEGINPROCESS(CLKK)BEGINIF CLKK'EVENT AND CLKK = '1' THEN --1HZ時鐘2分頻Div2CLK <= NOT Div2CLK;END IF;END PROCESS;PROCESS(CLKK, Div2CLK)BEGINIF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1'; --產生清零計數ELSE RST_CNT <= '0';END IF;END PROCESS;Load <= NOT Div2CLK;CNT_EN <= Div2CLK; END BEHAV; LIBRARY IEEE; --32位鎖存器 USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG32B ISPORT(LK: IN STD_LOGIC; DIN: IN STD_LOGIC_VECTOR(31 downto 0);DOUT: OUT STD_LOGIC_VECTOR(31 downto 0));END REG32B; ARCHITECTURE BEHAV OF REG32B IS BEGINPROCESS(LK,DIN)BEGINIF LK'EVENT AND LK='1' THEN DOUT<=DIN;END IF;END PROCESS; END BEHAV; LIBRARY IEEE; --32位計數器 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER32B ISPORT(FIN:IN STD_LOGIC; --時鐘信號CLR:IN STD_LOGIC; --清零信號ENABL:IN STD_LOGIC; --計數使能信號DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COUNTER32B; ARCHITECTURE BEHAV OF COUNTER32B ISSIGNAL CQI : STD_LOGIC_VECTOR(31 DOWNTO 0);BEGINPROCESS(FIN,CLR,ENABL)BEGINIF CLR='1' THEN CQI<=(OTHERS=>'0'); --清零ELSIF FIN'EVENT AND FIN='1' THENIF ENABL='1' THEN CQI<=CQI+1;END IF;END IF;END PROCESS;DOUT<=CQI;END BEHAV;

QUARTUS II代碼展示圖

頻率計仿真圖如圖所示

六、實驗要求

（1）選擇實驗電路模式5
（2）設計仿真文件，進行軟件驗證
（3）用VHDL程序設計方法實現8位16進制頻率計設計
（4）通過下載線下載到實驗系統上進行硬件測試驗證

七、實驗擴展

實驗內容2:將頻率計改為8位10進制頻率計,注意此設計電路的計數器必須是8個4位的10進制計數器，而不是1個。此外注意在測頻速度上給予優化。
八位十進制頻率計頂層文件：

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FREQTEST8_10 IS PORT(FSIN:IN STD_LOGIC;CLK1HZ:IN STD_LOGIC;DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END ENTITY FREQTEST8_10; ARCHITECTURE BEHAV OF FREQTEST8_10 IS COMPONENT CNT10 IS PORT(FIN,CLR,ENA:IN STD_LOGIC;CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT:OUT STD_LOGIC); END COMPONENT CNT10; COMPONENT REG32B IS PORT(LOAD:IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT REG32B; COMPONENT FTCTRL IS PORT(CLKK:IN STD_LOGIC;CNT_EN:OUT STD_LOGIC;RST_CNT:OUT STD_LOGIC;LOAD:OUT STD_LOGIC); END COMPONENT FTCTRL;SIGNAL EN,CL,LD:STD_LOGIC;SIGNAL CNT1,CNT2,CNT3,CNT4,CNT5,CNT6,CNT7,CNT8:STD_LOGIC;SIGNAL DQ:STD_LOGIC_VECTOR(31 DOWNTO 0); BEGINU0:FTCTRL PORT MAP(CLKK=>CLK1HZ,CNT_EN=>EN,RST_CNT=>CL,LOAD=>LD);U1:CNT10 PORT MAP(FIN=>FSIN,CLR=>CL,ENA=>EN,CQ=>DQ(3 DOWNTO 0),COUT=>CNT1);U2:CNT10 PORT MAP(CNT1,CL,EN,DQ(7 DOWNTO 4),CNT2);U3:CNT10 PORT MAP(CNT2,CL,EN,DQ(11 DOWNTO 8),CNT3);U4:CNT10 PORT MAP(CNT3,CL,EN,DQ(15 DOWNTO 12),CNT4);U5:CNT10 PORT MAP(CNT4,CL,EN,DQ(19 DOWNTO 16),CNT5);U6:CNT10 PORT MAP(CNT5,CL,EN,DQ(23 DOWNTO 20),CNT6);U7:CNT10 PORT MAP(CNT6,CL,EN,DQ(27 DOWNTO 24),CNT7);U8:CNT10 PORT MAP(CNT7,CL,EN,DQ(31 DOWNTO 28),CNT8);U9:REG32B PORT MAP(LOAD=>LD,DIN=>DQ(31 DOWNTO 0),DOUT=>DOUT); END ARCHITECTURE BEHAV;

十進制計數器示例程序：

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CNT10 IS PORT(FIN:IN STD_LOGIC;CLR:IN STD_LOGIC;ENA:IN STD_LOGIC;CQ:OUT INTEGER RANGE 0 TO 15;COUT:OUT STD_LOGIC); END ENTITY CNT10; ARCHITECTURE BEHAV OF CNT10 ISSIGNAL CQI:INTEGER RANGE 0 TO 15;BEGINPROCESS(FIN,CLR,ENA)ISBEGINIF CLR='1'THEN CQI<=0;ELSIF FIN'EVENT AND FIN='1'THENIF ENA='1'THENIF CQI<9 THEN CQI<=CQI+1;ELSE CQI<=0;END IF;END IF;END IF;END PROCESS; PROCESS(CQI) ISBEGINIF CQI=9 THEN COUT<='1';ELSE COUT<='0';END IF;END PROCESS;CQ<=CQI; END ARCHITECTURE BEHAV;

測頻控制電路示例程序：

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FTCTRL ISPORT (CLKK : IN STD_LOGIC;CNT_EN : OUT STD_LOGIC;RST_CNT : OUT STD_LOGIC;LOAD: OUT STD_LOGIC ); END FTCTRL; ARCHITECTURE BEHAV OF FTCTRL ISSIGNAL Div2CLK : STD_LOGIC; BEGINPROCESS( CLKK )BEGINIF CLKK'EVENT AND CLKK = '1' THENDiv2CLK <= NOT Div2CLK;END IF;END PROCESS;PROCESS(CLKK, Div2CLK)BEGINIF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1';ELSE RST_CNT <= '0';END IF;END PROCESS;LOAD <= NOT Div2CLK;CNT_EN <= Div2CLK; END BEHAV;

32位鎖存器示例代碼：

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG32B ISPORT(LOAD:IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END ENTITY REG32B; ARCHITECTURE BEHAV OF REG32B ISBEGINPROCESS(LOAD,DIN) ISBEGINIF LOAD'EVENT AND LOAD='1' THEN DOUT<=DIN;END IF;END PROCESS; END ARCHITECTURE BEHAV;

8位10進制頻率計仿真波形圖

管腳定義實況：

后續有時間會加更ing…

工程文件下載：
8位16進制頻率計設計源代碼
8位10進制頻率計設計源代碼

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