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typetitlereserved

AArch32 state	The ARM 32-bit Execution state that uses 32-bit general purpose registers, and a 32-bit program counter (PC), stack pointer (SP), and link register (LR). AArch32 Execution state provides a choice of two instruction sets, A32 and T32, previously called the ARM and Thumb instruction sets.	reserved
AArch64 state	The ARM 64-bit Execution state that uses 64-bit general purpose registers, and a 64-bit program counter (PC), stack pointer (SP), and exception link registers (ELR). AArch64 Execution state provides a single instruction set, A64.	reserved
EL0	The lowest Exception level. The Exception level that is used to execute user applications,in Non-secure state.	reserved
EL1	Privileged Exception level. The Exception level that is used to execute operating systems, in Non-secure state.	reserved
EL2	Hypervisor Exception level. The Exception level that is used to execute hypervisor code. EL2 is always in Non-secure state.	reserved
EL3	Secure Monitor Exception level. The Exception level that is used to execute Secure Monitor code, which handles the transitions between Non-secure and Secure states. EL3 is always in Secure state.	reserved
Function Identifier	A 32-bit integer that identifies which function is being invoked by this SMC or HVC call.Passed in R0 or W0 into every SMC or HVC call.	reserved
HVC	Hypervisor Call, an ARM assembler instruction that causes an exception that is taken synchronously into EL2.	reserved
Hypervisor	The hypervisor runs at the EL2 Exception level. It supports the execution of multiple EL1 Operating Systems.	reserved
Non-secure state	The ARM Execution state that restricts access to only the Non-secure system resources such as: memory, peripherals, and System registers.	reserved
OEM Original	Equipment Manufacturer. In this document, the final device manufacturer.PE Processing element. The abstract machine that is defined in the ARM architecture	reserved
Rx	Register; A32 native 32-bit register, A64 architectural register	reserved
S-EL0	The Secure EL0 Exception level, the Exception level that is used to execute trusted application code in Secure state	reserved
S-EL1	The Secure EL1 Exception level, the Exception level that is used to execute Trusted OS code in Secure state	reserved
Secure Monitor	The Secure Monitor is software that executes at the EL3 Exception level. It receives and handles Secure Monitor exceptions, and provides transitions between Secure state and Non-secure state	reserved
Secure state	The ARM Execution state that enables access to the Secure and Non-secure systems resources, such as: memory, peripherals, and System registers.	reserved
SiP	Silicon Partner，In this document, the silicon manufacturer.SMC Calling Convention Page 6 of 19 Copyright ? 2013, 2016 ARM Limited or its affiliates. All rights reserved	reserved
SMC	Secure Monitor Call. An ARM assembler instruction that causes an exception that is taken synchronously into EL3	reserved
SMCCC	SMC Calling Convention, this document	reserved
SMC32/HVC32	32-bit SMC and HVC calling convention	reserved
SMC64/HVC64	64-bit SMC and HVC calling convention	reserved
Wx	A64 32-bit register view	reserved
Xx	A64 64-bit register view	reserved
Trusted OS	The secure operating system running in the Secure EL1 Exception level. It supports the execution of trusted applications in Secure EL	reserved
reserved	reserved	reserved

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