計算機專業英語

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時間：2006/9/27 20:04:00?最新討論：2006/9/27 20:03:41

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我買了這本書，但是沒有每一單元后面的習題的答案和電子教案！能不能發給我一份！郵箱：adore_chenjinfu@yahoo.com.cn

例如第一個單元的11頁：

ISP is not as easy as it seemsAn embedded system capable of ISP means that a host computer can download firmware into flash memory through a communications channel. Although the channel of choice is typically a UART, it can be any communication channel that the MCU supports (Ethernet, J1850, CAN, HPIB, etc).As easy as this seems, there is a fundamental problem. You can't erase or write to the same flash memory from which you are executing code. If the MCU 's boot code and programming algorithms (ISP loader code) are stored in this flash memory, they will be unavailable to the MCU during ISP. Therefore, it is nearly impossible to implement ISP of flash memory under MCU control in an embedded system that contains only a single flash memory. It is absolutely necessary to use an additional independent memory to execute the ISC loader code.

Jumping the Hurdles There are major challenges that designers face when implementing ISP with external flash, which are:

Building the MCU-to-flash interface

Adding a second memory array from which the MCU can operate during ISP

Overcoming the inability of 8051 MCUs to write to program memory

Designing the MCU interface and adding a second memory array for ISP are related in that they can be affected by the level of integration of the flash memory device. A typical discrete solution will include a flash device, a second memory array for ISP, address latches, and a CLPD for address decoding, control logic and implementation of paging/segmentation schemes to enable ISP. The choice of the second memory array depends on the design requirements.

Using an SRAM for the second memory array offers the ability to update the boot and programming algorithms in addition to the application firmware. However, extra measures must be taken to recover from an interruption of power during ISP, which could render the system dysfunctional. While a separate ROM is the most stable and least expensive solution, it precludes any updates to the boot code or programming algorithms. The best choice is an EEPROM or second flash memory, as this ensures the integrity of the boot code and programming algorithms in the event of a power loss during ISP, while, at the same time offers the option of updating the code.

Finally, there are a number of highly integrated flash devices available today that integrate several memory arrays on a single substrate that can operate concurrently(read form one while writing to another).This is the ideal architecture for implementing ISP.

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