//此模塊實(shí)現(xiàn)頻率、相位可調(diào)的DDS信號(hào)輸出
//Fword越大，越快的的讓高位的address+1，Fword取0，那么則需要很長很長的時(shí)間address才會(huì)+1
//所以Fword相當(dāng)于步進(jìn)，步進(jìn)越大，頻率越快，步進(jìn)越小，頻率越小。
//---------------------------------------------------------------------------------
//pword 用于控制相位，取address的哪一個(gè)點(diǎn)作為初始值
//值得注意的是：pword必須設(shè)置為 2^N ,因?yàn)閍ddress是靠位溢出回到0地址的，否則，會(huì)導(dǎo)致每一個(gè)周期后就會(huì)有偏差，逐漸偏差擴(kuò)大

//理論部分:
/如果DDS的時(shí)鐘頻率為Fclk，
頻率控制字為1，則輸出頻率為Fout=BFclk/2^N,這個(gè)Fout頻率
就是多久才讓address+1的頻率，可知，如果N越大，
N就是指Fword_width，那么越慢讓address+1.
B就是fword，步進(jìn)越大，越快地讓address+1.*/

//下面實(shí)現(xiàn)quartus里面仿真

module DDS_module #( parameter Fword_width=32, parameter pword_width=12, parameter DA_data_width=12 ) ( input clk, input rst_n, input [Fword_width-1:0] Fword,//頻率控制字 input [pword_width-1:0] pword,//相位控制字 output DA_clk, output [DA_data_width:0] DA_data );reg [Fword_width-1:0] r_Fword;//頻率控制 always@ (posedge clk or negedge rst_n) beginif(!rst_n)r_Fword<=0;elser_Fword<=Fword; end//--------------------------- reg [Fword_width-1:0] address_reg;always @(posedge clk or negedge rst_n) beginif(!rst_n)address_reg<=0;elseaddress_reg<=address_reg+r_Fword;endreg [pword_width-1:0] r_pword;//偏移量 always @ (posedge clk or negedge rst_n) beginif(!rst_n)r_pword<=0;else r_pword<=pword; endwire [pword_width-1:0] rom_address;//相位控制 assign rom_address =address_reg[Fword_width-1:Fword_width-pword_width] + r_pword;//ROM ROM ROM_inst (.clock(clk),.address(rom_address), //mif文件，地址12位，4096個(gè)數(shù)，位寬12.q(DA_data)); endmodule

//下面是tb文件

// Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details.// ***************************************************************************** // This file contains a Verilog test bench template that is freely editable to // suit user's needs .Comments are provided in each section to help the user // fill out necessary details. // ***************************************************************************** // Generated on "11/03/2018 20:52:00"// Verilog Test Bench template for design : DDS_module // // Simulation tool : ModelSim (Verilog) // `timescale 1 ns/ 1 ps module DDS_module_vlg_tst(); reg [31:0] Fword; reg clk; reg [11:0] pword; reg rst_n; // wires wire DA_clk; wire [11:0]DA_data;initial begin #0 clk=0;#0 rst_n=0;#0 Fword=32'd262143;#0 pword=12'd511;#20 rst_n=1; end always #20 beginclk<=~clk; endDDS_module i1 ( // port map - connection between master ports and signals/registers .DA_clk(DA_clk),.DA_data(DA_data),.Fword(Fword),.clk(clk),.pword(pword),.rst_n(rst_n) ); endmodule

工程代碼如下：https://download.csdn.net/download/ciscomonkey/10763436

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