Operation condition And timing analysis
Operation condition 主要指芯片運行的環(huán)境的不同,在這里加上Interconnect net 模型.
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| Process derating factor? | This value is related to the scaling of device parameters resulting from variations in the fabrication process. A process number less than the nominal value usually results in smaller delays.? |
| Ambient temperature? | The chip temperature affects device delays. The temperature of the chip depends on several factors, including ambient air temperature, power consumption, package type, and cooling method.? |
| Supply voltage? | A higher supply voltage usually results in smaller delays.? |
| Interconnect model type? | This value defines an RC tree topology that PrimeTime uses to estimate net capacitance and resistance during prelayout analysis.? |
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當(dāng)Operation condition設(shè)置好只好,PT/DC/ICC/Encounter等可以根據(jù)R/C去計算pin-pin之間的延遲.
如何check Setup或者h(yuǎn)old就是analysis mode 的問題了.
主要包括以下三種:(源自User manual)
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Single operating condition mode – Uses a single set of delay parameters for the entire design, based on one set of process, temperature, and voltage conditions.
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On-chip variation (OCV) mode – Performs a conservative analysis that allows both minimum and maximum delays to apply to?different paths at the same time. For a setup check, it uses maximum delays for the launch clock path and data path, and minimum delays for the capture clock path. For a hold check, it uses minimum delays for the launch clock path and data path, and maximum delays for the capture clock path.
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Advanced on-chip variation (AOCV) mode – Determines derating factors based on metrics of path logic depth and the physical distance traversed by a particular path.
?? 可以看到在OCV中,capture clock path使用best case, data path 使用worst case(對于Setup檢查). 當(dāng)某一段path既是clock path又是data path的時候.這段path具有雙重的屬性.這樣更加的pessimistic. ?For a more accurate analysis, this pessimism can be corrected. For more
information, see Clock Reconvergence Pessimism Removal.
轉(zhuǎn)載于:https://www.cnblogs.com/hucs/p/3910960.html
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