視頻處理單元Video Processing Unit
VPU處理全局視頻處理，它包括時(shí)鐘門(mén)、塊復(fù)位線和電源域的管理。

缺少什么：

?完全重置整個(gè)視頻處理硬件塊

?VPU時(shí)鐘的縮放和設(shè)置

?總線時(shí)鐘門(mén)

?啟動(dòng)視頻處理硬件塊

?啟動(dòng)HDMI控制器和PHY

視頻處理單元

顯示控制器由以下幾個(gè)組件組成：
DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
| vd1 _______ _____________ _________________ | |
D |-------| |----| | | | | HDMI PLL |
D | vd2 | VIU | | Video Post | | Video Encoders |<—|-----VCLK |
R |-------| |----| Processing | | | | |
| osd2 | | | |—| Enci ----------|----|-----VDAC------|
R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
A | osd1 | | | Blenders | | Encl ----------|----|---------------|
M |-------||----|| || | |
|______________________________________||
Video Input Unit
VIU handle像素掃描和基本顏色空間轉(zhuǎn)換，包括以下功能：
OSD1 RGB565/RGB888/xRGB8888 scanout
? RGB conversion to x/cb/cr
? Progressive or Interlace buffer scanout
? OSD1 Commit on Vsync
? HDR OSD matrix for GXL/GXM
What is missing :
? BGR888/xBGR8888/BGRx8888/BGRx8888 modes
? YUV4:2:2 Y0CbY1Cr scanout
? Conversion to YUV 4:4:4 from 4:2:2 input
? Colorkey Alpha matching
? Big endian scanout
? X/Y reverse scanout
? Global alpha setup
? OSD2 support, would need interlace switching on vsync
? OSD1 full scaling to support TV overscan
Video Post Processing
VPP Handles有關(guān)VIU掃描后的所有后處理，包括以下模塊:
? Postblend, Blends the OSD1 only
We exclude OSD2, VS1, VS1 and Preblend output
? Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
use it only for interlace scanout
? Intermediate FIFO with default Amlogic values
What is missing :
? Preblend for video overlay pre-scaling
? OSD2 support for cursor framebuffer
? Video pre-scaling before postblend
? Full Vertical/Horizontal OSD scaling to support TV overscan
? HDR conversion
Video Encoder
VENC將像素編碼處理為輸出格式。包括以下編碼 :
? CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
? TMDS/HDMI Encoding via ENCI_DIV and ENCP
? Setup of more clock rates for HDMI modes
What is missing :
? LCD Panel encoding via ENCL
? TV Panel encoding via ENCT
VENC paths :
_____ _____ ____________________
vd1—| |-| | | VENC /---------|----VDAC
vd2—| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
osd1–| |-| | | \ | X–HDMI-TX
osd2–||-|| | |-ENCP–ENCP_DVI-|-|
| | |
| --ENCL-----------|----LVDS
|____________________|
ENCI設(shè)計(jì)用于PAl或NTSC編碼，可以直接通過(guò)VDAC進(jìn)行CVBS編碼，也可以通過(guò)ENCI\U DVI編碼器，進(jìn)行HDMI編碼。ENCP設(shè)計(jì)用于漸進(jìn)編碼，但也可以生成1080i交錯(cuò)像素，最初設(shè)計(jì)用于對(duì)VDAC的像素編碼，以輸出RGB ou YUV模擬輸出。輸出通過(guò)用于HDMI的ENCP\U DVI編碼器。ENCL LVDS編碼器未實(shí)現(xiàn)。
ENCI和ENCP編碼器，需要為每個(gè)支持的模式專(zhuān)門(mén)定義參數(shù)，因此不能從標(biāo)準(zhǔn)視頻timings來(lái)確定。
ENCI-end-ENCP-DVI編碼器更通用，可以從ENCI或ENCP生成的像素?cái)?shù)據(jù)，生成任何時(shí)序，可以使用標(biāo)準(zhǔn)視頻時(shí)序作為HW參數(shù)的源。
Video Clocks
VCLK是一個(gè)專(zhuān)用PLL的“像素時(shí)鐘”頻率發(fā)生器。包括以下編碼：
CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
? HDMI Pixel Clocks generation
What is missing :
? Genenate Pixel clocks for 2K/4K 10bit formats
Clock generator scheme :

---

| | | | | |–ENCI
| HDMI PLL |-| PLL_DIV |— VCLK–| |–ENCL
|_| || \ | MUX |–ENCP
–VCLK2-| |–VDAC
|_____|–HDMI-TX
Final clocks can take input for either VCLK or VCLK2, but VCLK is the preferred path for HDMI clocking and VCLK2 is the preferred path for CVBS VDAC clocking.
VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.
The PLL_DIV can achieve an additional fractional dividing like 1.5, 3.5, 3.75… to generate special 2K and 4K 10bit clocks.
HDMI Video Output
HDMI Output is composed of :
? A Synopsys DesignWare HDMI Controller IP
? A TOP control block controlling the Clocks and PHY
? A custom HDMI PHY in order convert video to TMDS signal

---

| HDMI TOP |<= HPD
||
| | |
| Synopsys HDMI | HDMI PHY |=> TMDS
| Controller |________________|
||<=> DDC
HDMI機(jī)頂盒僅支持HPD感測(cè)。Synopsys HDMI控制器，中斷頂部塊中斷路由。通過(guò)一對(duì)addr+read/write讀/寫(xiě)寄存器以及頂層模塊，與Synopsys HDMI控制器進(jìn)行通信。HDMI PHY由HHI寄存器配置。
像素?cái)?shù)據(jù)以4:4:4格式，從VENC塊到達(dá)，VPU HDMI mux為576i或480i格式，選擇ENCI編碼器，或?yàn)樗衅渌袷?#xff08;包括隔行高清格式），選擇ENCP編碼器。VENC使用ENCI或ENCP編碼器頂部的DVI編碼器，為HDMI控制器生成DVI定時(shí)。
GXBB、GXL和GXM嵌入了Synopsys DesignWare HDMI TX IP版本2.01a，帶有HDCP和I2C&S/PDIF音頻源接口。
It handle the following features :
? HPD Rise & Fall interrupt
? HDMI Controller Interrupt
? HDMI PHY Init for 480i to 1080p60
? VENC & HDMI Clock setup for 480i to 1080p60
? VENC Mode setup for 480i to 1080p60
What is missing :
? PHY, Clock and Mode setup for 2k && 4k modes
? SDDC Scrambling mode for HDMI 2.0a
? HDCP Setup
? CEC Management

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