有一個灰常郁悶的問題。。。

module CLK_Generater(
??????????????????? input??????? CLOCK_100,
??????????????????? input??????? RST_n,
??????????????????? input??????? Key,
??????????????????? output??? reg??? [3:0]??? CLK_DivChoose,

??????????????????? );
reg???? [19:0]??? count;??????????? //Delay_10ms
reg???????????? CLK_100Hz;???????? //100HZ(10ms)時鐘信
reg???? [2:0]??? state;????????? //狀態標志

reg??????? [16:0]??? cnt;
reg??????? [17:0]??? Div_cnt;

always @(posedge CLOCK_100 or negedge RST_n)
begin
??? if(!RST_n)
??????? begin
??????? CLK_100Hz<=0;
??????? count<=0;
??????? end
??? else
??????? begin
??????? if(count<20'd1000000)
??????????? begin
??????????? count<=count+1'b1;
??????????? CLK_100Hz<=CLK_100Hz;
??????????? end
??????? else
??????????? begin
??????????? count<=0;
??????????? CLK_100Hz<=~CLK_100Hz;
??????????? end???
??????? end
end

always@(posedge CLK_100Hz or negedge RST_n)
begin
??? if(!RST_n)
??????? CLK_DivChoose <= 4'h0;
??? else
??????? begin
??????? case(state)??????????????? //按鍵，不按下去的時候是VCC高，按下去的時候是GND低
??????? 0:
??????????? begin
??????????? if(!Key)??????????? //檢測鍵盤是否被按下(Delay_5ms)
??????????????? state <= 1;
??????????? else
??????????????? state <= 0;??????? //未按下，循環檢測
??????????? end
??????? 1:
??????????? begin
??????????? if(!Key)??????????? //檢測鍵盤是否真的被按下，還是抖動(消抖動(Delay_5ms))
??????????????? state <= 2;??????? //檢測到不是抖動，進行下一步操作
??????????? else
??????????????? state <= 0;??????? //是抖動，回去繼續檢測按鍵
??????????? end
??????? 2:
??????????? begin???????????
??????????? CLK_DivChoose <= CLK_DivChoose+1'b1;
??????????? state <= 3;??????????? //只進行加1操作，不連加???????????
??????????? end
??????? 3:
??????????? begin
??????????? if(Key)??????????????? //松手(VCC)檢測，有可能是抖動
??????????????? state <= 4;
??????????? else??????????????? //檢測到還是(GND)低電平，未松手
??????????????? state <= 3;
??????????? end
??????? 4:
??????????? begin
??????????? if(Key)??????????????? //松手(VCC)檢測，有可能是抖動
??????????????? state <= 0;
??????????? else
??????????????? state <= 4;??????? //檢測到還是(GND)低電平，未松手
??????????? end
??????? endcase
??????? end
end

endmodule

CLK_DivChoose 同時接到4個LED

轉載于:https://www.cnblogs.com/FPGA_DSP/archive/2011/02/09/1950416.html

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