Altera的几个常用的Synthesis attributes（转载）
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各廠商綜合工具，對HDL綜合時都定義了一些綜合屬性這些屬性可指定a declaration,a module item,a statement, or a port connection?不同的綜合方式。
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語法為：
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/* synthesis, <any_company_specific_attribute = value_or_optional_value */
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下面就是Altera的幾個常用的Synthesis attributes
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Noprune
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?A Verilog HDL synthesis attribute that prevents the Quartus II software from removing a register that does not directly or indirectly feed a top-level output or bidir pin.
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For example:
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reg reg1 /* synthesis noprune */;
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keep
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?A Verilog HDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular net when optimizing combinational logic.
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For example:
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wire keep_wire /* synthesis keep */;
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preserve
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?A Verilog HDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular register when eliminating redundant registers or registers with constant drivers.
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For example:
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reg reg1 /* synthesis preserve */;
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ram_init_file
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A Verilog HDL synthesis attribute that specifies initial contents of an inferred memory.
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For example:
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reg [7:0] mem[0:255] /* synthesis ram_init_file = " my_init_file.mif" */;
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ramstyle
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A Verilog HDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred RAM.
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M512", "M4K", "M9K", "M144K", "MLAB", "M-RAM”
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For example:
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reg [0:7] my_ram[0:63] /* synthesis ramstyle = "M512" */;
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translate_off??or??translate_on
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?Verilog HDL synthesis directives that direct Analysis & Synthesis to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.
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For example:
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parameter tpd = 2;??// Generic delays
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// synthesis translate_off
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#tpd;
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// synthesis translate_on
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關于狀態機有下面三個綜合屬性:
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full_case
?A Verilog HDL synthesis attribute that directs Analysis & Synthesis to treat unspecified state values in a Verilog Design File Case Statement as don't care values, and therefore to treat the Case Statement as "full".
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僅用于Verilog ,與case 語句一起使用表明所有可能的狀態都已經給出不需要其他邏輯保持信號的值.
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module full_case (a, sel, y);
?? input [3:0] a;
?? input [1:0] sel;
?? output y;
?? reg y;
?? always @(a or sel)??????????????? case (sel)????? // synthesis full_case?
???????? 2'b00: y="a"[0];
???????? 2'b01: y="a"[1];
???????? 2'b10: y="a"[2];
????? endcase
endmodule
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?parallel_case
?A Verilog HDL synthesis attribute that directs Analysis & Synthesis to implement parallel logic rather than a priority scheme for all case item expressions in a Verilog Design File Case Statement.
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僅用于Verilog ,與case 語句一起使用強制生成一個并行的多路選擇結構而不是一個優
先譯碼結構.
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?module parallel_case (sel, a, b, c);
?? input [2:0] sel;
?? output a, b, c;
?? reg a, b, c;
?? always @(sel)????????????????? begin
????? {a, b, c} = 3'b0;
????? casez (sel)??????????????? // synthesis parallel_case?
???????? 3'b1??: a = 1'b1;
???????? 3'b?1?: b = 1'b1;
???????? 3'b??1: c = 1'b1;
????? endcase
?? end
endmodule
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syn_encoding
?A Verilog HDL synthesis attribute that determines how the Quartus II software should encode the states of an inferred state machine.
?強制重新狀態機的狀態編碼方式.有default,one-hot,sequential,gray,johnson,compact,user幾種編碼方式
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(* syn_encoding = "user" *) reg [1:0] state;
parameter init = 0, last = 3, next = 1, later = 2;
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always @ (state) begin
case (state)
init:
out = 2'b01;
next:
out = 2'b10;
later:
out = 2'b11;
last:
out = 2'b00;
endcase
end
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In the above example, the states will be encoded as follows:
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init?? = "00"
last?? = "11"
next?? = "01"
later?? = "10"
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轉載于:https://www.cnblogs.com/lianjiehere/p/4292704.html
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